参数资料
型号: AT89C51SND2C-7FTUL
厂商: Atmel
文件页数: 28/160页
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
标准包装: 260
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外围设备: 音频,I²S,MP3,PCM,POR,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TFBGA
包装: 托盘
其它名称: AT89C51SND2C7FTUL
DS785UM1
5-31
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
I2SClkDiv
Address:
0x8093_008C - Read/Write, Software locked
Default:
0x0000_0000
Definition:
Configures the I2S block audio clocks MCLK, SCLK, and LRCLK.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
SENA:
Enable audio clock generation.
SLAVE:
I2S slave. Configures the I2S clock system to operate as a
slave. SCLK and LRCLK are chip inputs. The clock
configuration controls in this register are ignored in slave
mode.
ORIDE:
Override I2S master configuration.
1 - Override the SAI_MSTR_CLK_CFG from the I2S block
and use the I2SClkDiv Register settings.
0 - Use the I2S SAI_MSTR_CLK_CFG signals.
DROP:
Drop SCLK clocks.
1 - When in 64x mode, drop 8 SCLKs.
0 - Do not drop SCLKs.
SPOL:
SCLK polarity. Defines the SCLK edge that aligns to
LRCLK transitions.
1 - LRCLK transitions on the falling SCLK edge.
0 - LRCLK transitions on the rising SCLK edge.
LRDIV:
LRCLK divide select.
00 - LRCK = SCLK / 32
01 - LRCK = SCLK / 64
10 - LRCK = SCLK / 128
11 - Reserved
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SENA
SLAVE
ORIDE
RSVD
DROP
SPOL
LRDIV
SDIV
15
14
13
12
11
10
987654
3210
MENA
ESEL
PSEL
RSVD
PDIV
RSVD
MDIV
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