参数资料
型号: AT89C51SND2C-7FTUL
厂商: Atmel
文件页数: 26/160页
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
标准包装: 260
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外围设备: 音频,I²S,MP3,PCM,POR,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TFBGA
包装: 托盘
其它名称: AT89C51SND2C7FTUL
DS785UM1
5-29
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
SWRST:
Software reset. A one to zero transition of this bit initiates
a software reset.
VidClkDiv
Address:
0x8093_0084 - Read/Write, Software locked
Default:
0x0000_0000
Definition:
Configures video clock for the raster engine. Selects input to VCLK dividers
from either PLL1 or PLL2, and defines a programmable divide value.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
VENA:
Enable VCLK divider.
ESEL:
External clock source select.
0 - use the external XTALI clock input as the clock source.
1 - use one of the internal PLLs selected by PSEL as the
clock source.
PSEL:
PLL source select.
1 - select PLL2 as the clock source.
0 - select PLL1 as the clock source.
PDIV:
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
VDIV:
VCLK divider value. Forms a divide-by-N of the pre-divide
clock output. VCLK is the source clock divided by PDIV
divided by N. Must be at least two.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
987654
3210
VENA
ESEL
PSEL
RSVD
PDIV
RSVD
VDIV
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