参数资料
型号: AT89C51SND2C-7FTUL
厂商: Atmel
文件页数: 142/160页
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
标准包装: 260
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外围设备: 音频,I²S,MP3,PCM,POR,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TFBGA
包装: 托盘
其它名称: AT89C51SND2C7FTUL
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
41
EP7312
High-Performance, Low-Power System on Chip
C14
VSSIO
Pad ground
I/O ground
C15
nPOR
Schmitt
I
Power-on reset input
C16
nEXTPWR
I
External power supply sense input
D1
WRITE/nSDRAS
1
Low
O
Transfer direction / SDRAM RAS signal output
D2
EXPRDY
1
I
Expansion port ready input
D3
VSSIO
Pad ground
I/O ground
D4
VDDIO
Pad power
Digital I/O power, 3.3V
D5
nCS[2]
1
High
O
Chip select 2
D6
nMWE/nSDWE
1
High
O
ROM, expansion write enable/ SDRAM write enable control signal
D7
nSDCS[0]
1
High
O
SDRAM chip select 2
D8
CL[2]
1
Low
O
LCD pixel clock out
D9
VSSRTC
Core ground
Real time clock ground
D10
D[4]
1
Low
I/O
Data I/O
D11
nPWRFL
I
Power fail sense input
D12
MOSCIN
I
Main oscillator input
D13
VDDIO
Pad power
Digital I/O power, 3.3V
D14
VSSIO
Pad ground
I/O ground
D15
D[7]
1
Low
I/O
Data I/O
D16
D[8]
1
Low
I/O
Data I/O
E1
RXD[2]
I
UART 2 receive data input
E2
PB[7]
1
Input
IGPIO port B
E3
TDI
with p/u*
I
JTAG data input
E4
WORD
1
Low
O
Word access select output
E5
VSSIO
Pad ground
I/O ground
E6
nCS[0]
1
High
O
Chip select 0
E7
SDQM[2]
2
Low
O
SDRAM byte lane mask
E8
FRM
1
Low
O
LCD frame synchronization pulse
E9
A[0]
2
Low
O
System byte address
E10
D[5]
1
Low
I/O
Data I/O
E11
VSSOSC
Oscillator ground
PLL ground
E12
VSSIO
Pad ground
I/O ground
E13
nMEDCHG/nBROM
I
Media change interrupt input / internal ROM boot enable
E14
VDDIO
Pad power
Digital I/O power, 3.3V
E15
D[9]
1
Low
I/O
Data I/O
E16
D[10]
1
Low
I/O
Data I/O
F1
PB[5]
1
Input
IGPIO port B
F2
PB[3]
1
Input
IGPIO port B
F3
VSSIO
Pad ground
I/O ground
F4
TXD[2]
1
High
O
UART 2 transmit data output
F5
RUN/CLKEN
1
Low
O
Run output / clock enable output
F6
VSSIO
Pad ground
I/O ground
F7
SDCKE
2
Low
O
SDRAM clock enable output
F8
DD[3]
1
Low
O
LCD serial display data
F9
A[1]
2
Low
O
System byte address
F10
D[6]
1
Low
I/O
Data I/O
F11
VSSRTC
RTC ground
Real time clock ground
F12
BATOK
I
Battery OK input
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
Description
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