参数资料
型号: AT89C51SND2C-7FTUL
厂商: Atmel
文件页数: 160/160页
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
标准包装: 260
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外围设备: 音频,I²S,MP3,PCM,POR,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TFBGA
包装: 托盘
其它名称: AT89C51SND2C7FTUL
9
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 4-11.
A/D Converter Signal Description (AT8XSND2CMP3B only)
Table 4-12.
External Access Signal Description
Note:
1. For ROM/Flash/ROMless Dice product versions only.
Table 4-13.
System Signal Description
Signal
Name
Type
Description
Alternate
Function
AIN1:0
I
A/D Analog Inputs
-
ADCREFP
I
Analog Positive Voltage Reference Input
-
ADCREFN
I
Analog Negative Voltage Reference Input
-
Signal
Name
Type
Description
Alternate
Function
A15:8
I/O
Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the IDE
interface.
P0.7:0
ALE
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A7:0. An external latch is used to demultiplex
the address from address/data bus.
-
ISP
I/O
ISP Enable Input (AT89C51SND2C Only)
This signal must be held to GND through a pull-down resistor at the falling
reset to force execution of the internal bootloader.
-
RD
O
Read Signal
Read signal asserted during external data memory read operation.
P3.7
WR
O
Write Signal
Write signal asserted during external data memory write operation.
P3.6
EA(1)
I
External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations 0000H to FFFFH (RD).
-
Signal
Name
Type
Description
Alternate
Function
RST
I
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than V
IL is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset
by connecting a capacitor between this pin and V
DD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the
chip to normal operation.
-
TST
I
Test Input
Test mode entry signal. This pin must be set to V
DD.
-
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