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| 型号： | B80547RE083256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 3060 MHz, MICROPROCESSOR, PBGA775 |
| 封装： | FLIP CHIP, LGA-775 |
| 文件页数： | 64/94页 |
| 文件大小： | 2796K |
| 代理商： | B80547RE083256 |
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Datasheet
67
Land Listing and Signal Descriptions
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins/lands of all processor FSB
agents. For a locked sequence of transactions, LOCK# is asserted from
the beginning of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor FSB, it will wait until it observes LOCK# de-asserted. This
enables symmetric agents to retain ownership of the processor FSB
throughout the bus locked operation and ensure the atomicity of lock.
MCERR#
Input/
Output
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable
error without a bus protocol violation. It may be driven by all processor FSB
agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined by the following options:
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction
after it observes an error.
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, refer to the IA-32
Software Developer’s Manual, Volume 3: System Programming Guide.
MS_ID[1:0]
Output
These signals are provided to indicate the Market Segment for the
processor and may be used for future processor compatibility or for keying.
PC_REQ#
Output
This signal provides an external bus indicator that the processor is done
with the DRAM page and that the DRAM page could/should be closed.
PC_REQ# is not a feature of the Celeron D processor in the 775-land
package. It is included here for future processor compatibility.
PROCHOT#
Input/
Output
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor has
reached its maximum safe operating temperature. This indicates that the
processor Thermal Control Circuit (TCC) has been activated, if enabled. As
an input, assertion of PROCHOT# by the system will activate the TCC, if
enabled. The TCC will remain active until the system de-asserts
PROCHOT#. See Section 5.2.4 for more details.
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor requires
this signal to be a clean indication that the clocks and power supplies are
stable and within their specifications. ‘Clean’ implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the
time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins/lands
of all processor FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a
details on parity checking of these signals.
Table 4-3. Signal Description (Sheet 6 of 9)
Name
Type
Description
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