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参数资料
| 型号： | BU-65743F3-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 18/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-200 |
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Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
there is no explicit limit to the number of messages that may be
processed in a frame. In both modes, it is possible to program for
either single frame or frame auto-repeat operation. In the auto-
repeat mode, the frame repetition rate may be controlled either
internally, using a programmable BC frame timer, or from an
external trigger input.
ENHANCED BC MODE: MESSAGE SEQUENCE CONTROL
One of the major new architectural features of the PCI Mini-ACE
Mark3/Micro-ACE TE series is its advanced capability for BC
message sequence control. The PCI Mini-ACE Mark3/Micro-
ACE TE supports highly autonomous BC operation, which great-
ly offloads the operation of the host processor.
The operation of the PCI Mini-ACE Mark3/Micro-ACE TE's mes-
sage sequence control engine is illustrated in FIGURE 2. The BC
message sequence control involves an instruction list pointer reg-
ister; an instruction list which contains multiple 2-word entries; a
message control/status stack, which contains multiple 8-word or
10-word descriptors; and data blocks for individual messages.
The initial value of the instruction list pointer register is initialized
by the host processor (via Register 0D), and is incremented by
the BC message sequence processor (host readable via
Register 03). During operation, the message sequence control
processor fetches the operation referenced by the instruction list
pointer register from the instruction list.
Note that the pointer parameter referencing the first word of a
message's control/status block (the BC Control Word) must con-
tain an address value that is modulo 8. Also, note that if the
message is an RT-to-RT transfer, the pointer parameter must
contain an address value that is modulo 16.
OP CODES
The instruction list pointer register references a pair of words in
the BC instruction list: an op code word, followed by a parameter
word. The format of the op code word, which is illustrated in FIG-
URE 3, includes a 5-bit op code field and a 5-bit condition code
field. The op code identifies the instruction to be executed by the
BC message sequence controller.
Most of the operations are conditional, with execution dependent
on the contents of the condition code field. Bits 3-0 of the condi-
tion code field identifies a particular condition. Bit 4 of the condi-
tion code field identifies the logic sense ("1" or "0") of the select-
ed condition code on which the conditional execution is depen-
dent. TABLE 52 lists all the op codes, along with their respective
mnemonic, code value, parameter, and description. TABLE 53
defines all the condition codes.
Eight of the condition codes (8 through F) are set or cleared as the
result of the most recent message. The other eight are defined as
"General Purpose" condition codes GP0 through GP7. There are
three mechanisms for programming the values of the General
Purpose Condition Code bits: (1) They may be set, cleared, or tog-
gled by the host processor, by means of the BC GENERAL PUR-
POSE FLAG REGISTER; (2) they may be set, cleared, or toggled
by the BC message sequence control processor, by means of the
GP Flag Bits (FLG) instruction; and (3) GP0 and GP1 only (but
none of the others) may be set or cleared by means of the BC
message sequence control processor's Compare Frame Timer
(CFT) or Compare Message Timer (CMT) instructions.
The host processor also has read-only access to the BC condi-
tion codes by means of the BC CONDITION CODE REGISTER.
Note that four (4) instructions are unconditional. These are
Compare to Frame Timer (CFT), Compare to Message Timer
(CMT), GP Flag Bits (FLG), and Execute and Flip (XQF). For
these instructions, the Condition Code Field is "don't care". That
is, these instructions are always executed, regardless of the
result of the condition code test.
All of the other instructions are conditional. That is, they will only be
executed if the condition code specified by the condition code field
in the op code word tests true. If the condition code field tests false,
the instruction list pointer will skip down to the next instruction.
As shown in TABLE 52, many of the operations include a single-
word parameter. For an XEQ (execute message) operation, the
parameter is a pointer to the start of the message’s Control /
Status block. For other operations, the parameter may be an
address, a time value, an interrupt pattern, a mechanism to set
or clear general purpose flag bits, or an immediate value. For
several op codes, the parameter is "don't care" (not used).
As described above, some of the op codes will cause the mes-
sage sequence control processor to execute messages. In this
case, the parameter references the first word of a message
Control/Status block. With the exception of RT-to-RT transfer
messages, all message status/control blocks are eight words
long: a block control word, time-to-next-message parameter,
data block pointer, command word, status word, loopback word,
block status word, and time tag word.
In the case of an RT-to-RT transfer message, the size of the message
control/status block increases to 16 words. However, in this case, the
last six words are not used; the ninth and tenth words are for the sec-
ond command word and second status word.
FIGURE 3. BC OP CODE FORMAT
15
10
11
12
13
14
5
6
7
8
9
0
1
2
3
4
Odd Parity
0
OpCode Field
1
0
Condition Code Field
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