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参数资料
| 型号： | BU-65743F3-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 30/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-200 |
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36
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
Mark3/Micro-ACE TE RT continues to write received data words
to the upper half of the buffer.
Interrupt status queue. The PCI Mini-ACE Mark3/Micro-ACE
TE RT, Monitor, and combined RT/Monitor modes include the
capability for generating an interrupt status queue. As illustrated
in FIGURE 9, this provides a chronological history of interrupt
generating events and conditions. In addition to the Interrupt
Mask Register, the Interrupt Status Queue provides additional fil-
tering capability, such that only valid messages and/or only invalid
messages may result in the creation of an entry to the Interrupt
Status Queue. Queue entries for invalid and/or valid messages
may be disabled by means of bits 8 and 7 of configuration regis-
ter #6.
The pointer to the Interrupt Status Queue is stored in the
INTERRUPT VECTOR QUEUE POINTER REGISTER (register
address 1F). This register must be initialized by the host, and is
subsequently incremented by the RT message processor. The
interrupt status queue is 64 words deep, providing the capability
to store entries for up to 32 messages.
The queue rolls over at addresses of modulo 64. The events that
result in queue entries include both message-related and non-
message-related events. Note that the Interrupt Vector Queue
Pointer Register will always point to the next location (modulo 64)
following the last vector/pointer pair written by the PCI Mini-ACE
Mark3/Micro-ACE TE RT, Monitor, or RT/Monitor.
Each event that causes an interrupt results in a two-word entry
to be written to the queue. The first word of the entry is the inter-
rupt vector. The vector indicates which interrupt event(s)/condi-
tion(s) caused the interrupt.
The interrupt events are classified into two categories: message
interrupt events and non-message interrupt events. Message-
based interrupt events include End-of-Message, Selected mode
code, Format error, Subaddress control word interrupt, RT
Circular buffer Rollover, Handshake failure, RT Command stack
rollover,
transmitter
timeout,
MT
Data
Stack
rollover,
MT Command Stack rollover, RT Command Stack 50% rollover,
MT Data Stack 50% rollover, MT Command Stack 50% rollover,
and RT Circular buffer 50% rollover. Non-message interrupt
events/conditions include time tag rollover, RT address parity
error, RAM parity error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates
whether the entry is for a message interrupt event (if bit 0 is logic
"1") or a non-message interrupt event (if bit 0 is logic "0"). It is not
possible for one entry on the queue to indicate both a message
interrupt and a non-message interrupt.
As illustrated in FIGURE 9, for a message interrupt event, the para-
meter word is a pointer. The pointer will reference the first word of the
RT or MT command stack descriptor (i.e., the Block Status Word).
For a RAM Parity Error non-message interrupt, the parameter
will be the RAM address where the parity check failed. For the
RT address Parity Error, and Time Tag rollover non-message
interrupts, the parameter is not used; it will have a value of 0000.
If enabled, an INTERRUPT STATUS QUEUE ROLLOVER inter-
rupt will be issued when the value of the queue pointer address
rolls over at a 64-word address boundary.
RT COMMAND ILLEGALIZATION
The PCI Mini-ACE Mark3/Micro-ACE TE provides an internal
mechanism for RT Command Word illegalizing. By means of a
256-word area in shared RAM, the host processor may desig-
nate that any message be illegalized, based on the command
word T/R bit, subaddress, and word count/mode code fields. The
PCI Mini-ACE Mark3/Micro-ACE TE illegalization scheme pro-
vides the maximum in flexibility, allowing any subset of the 4096
possible combinations of broadcast/own address, T/R bit, sub-
address, and word count/mode code to be illegalized.
The address map of the PCI Mini-ACE Mark3/Micro-ACE TE's
illegalizing table is illustrated in TABLE 57.
BUSY BIT
The PCI Mini-ACE Mark3/Micro-ACE TE RT provides two differ-
ent methods for setting the Busy status word bit: (1) globally, by
means of Configuration Register #1; or (2) on a T/R-bit/subad-
dress basis, by means of a RAM lookup table. If the host CPU
asserts the BUSY bit low in Configuration Register #1, the PCI
Mini-ACE Mark3/Micro-ACE TE RT will respond to all non-broad-
cast commands with the Busy bit set in its RT Status Word.
Alternatively, there is a Busy lookup table in the PCI Mini-ACE
Mark3/Micro-ACE TE shared RAM. By means of this table, it is pos-
sible for the host processor to set the busy bit for any selectable sub-
set of the 128 combinations of broadcast/own address, T/R bit, and
subaddress.
If the busy bit is set for a transmit command, the PCI Mini-ACE
Mark3/Micro-ACE TE RT will respond with the busy bit set in the
status word, but will not transmit any data words. If the busy bit is
set for a receive command, the RT will also respond with the busy
status bit set. There are two programmable options regarding the
reception of data words for a non-mode code receive command for
which the RT is busy: (1) to transfer the received data words to
shared RAM; or (2) to not transfer the data words to shared RAM.
RT ADDRESS
The PCI Mini-ACE Mark3/Micro-ACE TE offers several different
options for designating the Remote Terminal address. These
include the following: (1) hardwired, by means of the 5 RT
ADDRESS inputs, and the RT ADDRESS PARITY input; (2) by
means of the RT ADDRESS (and PARITY) inputs, but latched via
hardware, on the rising edge of the RT_AD_LAT input signal; (3)
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