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参数资料
| 型号： | BU-65743F3-200 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 51/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-200 |
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55
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
INCMD (O)/
MCRST (O)
19
In-command or Mode Code Reset. The function of this pin is controlled by bit 0 of Configuration
Register #7, MODE CODE RESET / INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or Selective
Message Monitor modes, INCMD is asserted low whenever a message is being processed by
the PCI Mini-ACE Mark3/Micro-ACE TE. In Word Monitor mode, INCMD will be asserted low for
as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1", MCRST
will be active. In this case, MCRST will be asserted low for two clock cycles following receipt of
a Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this signal is
inoperative; i.e., in this case, it will always output a value of logic "1".
E8
TABLE 74. MISCELLANEOUS SIGNALS
DESCRIPTION
BALL
5V
PIN
C9
BALL
3V
SIGNAL NAME
TAG_CLK (I)
23
Input (5V tolerant) for optional external tag clock. No connection needed if internal tag clock is
used. Maximum TAG_CLK frequency is 1/44th of the 1553_CLK input.
D18
F14
SLEEP_IN (I)
14
Sleep input for both 3.3V transceivers. SLEEP_IN = 1 puts the 3.3V transceivers in sleep mode
(receiver and transmitter disabled).
--
R4
1553_CLK (I)
78
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
D8
B7
TX_INH A/B
(I)
18
Transmitter inhibit input (5V tolerant) for the Channel A and Channel B MIL-STD-1553 transmit-
ters. For normal operation, this input should be connected to logic "0". To force a shutdown of
Channel A and Channel B, a value of logic "1" should be applied to the TX_INH input.
F10
F8
MSTCLR
(RST#) (I)
25
Master Clear. Negative true Reset input, normally asserted low following power turn-on. This
input conforms to PCI RST# convention.
B11
R18
RTBOOT (I)
F7
If RTBOOT is connected to Logic "0" the PCI Micro ACE TE will initialize in RT mode with the Busy sta-
tus word bit set following power turn on. Received data will not be stored because the “BUSY RECEIVE
TRANSFER DISABLE” bit will also be set following power turn on. In addition, CLK_SEL_0 and
CLK_SEL_1 are enabled and they select the divider for the 1553 clock circuitry:
TABLE 75. MISCELLANEOUS SIGNALS, BGA ONLY
SIGNAL NAME
DESCRIPTION
BALL
3V XCVR
C12
BALL
5V XCVR
CLK_SEL1
CLK_SEL0
1553 CLOCK FREQUENCY
0
10 MHz
0
1
20 MHz
1
0
12 MHz
1
16 MHz
1553 CLOCK SELECT 0, ACTIVE ONLY WHEN RTBOOT = 0
CLK_SEL_0 (I)
L14
M18
1553 CLOCK SELECT 1, ACTIVE ONLY WHEN RTBOOT = 0
CLK_SEL_1 (I)
E14
B15
相关PDF资料 |
PDF描述 |
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| BU-65863F3-220 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
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| BU-65863B8-E02 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA324 |
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| BU1003 | POWER TRANSISTOR |
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