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参数资料
| 型号： | BX80525U533512E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, MICROPROCESSOR, XMA |
| 文件页数： | 11/94页 |
| 文件大小： | 898K |
| 代理商： | BX80525U533512E |
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Pentium
III Processor at 450 MHz, 500 MHz, 533B MHz, 550 MHz, 600/600B MHz
Datasheet
19
The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5 V. The CMOS,
APIC, and TAP outputs are open drain and should be pulled high to 2.5 V. This ensures not only
correct operation for current Pentium III processors, but compatibility with future Pentium III
processors as well.
The groups and the signals contained within each group are shown in Table 4. Refer to Section 7.0
for a description of these signals.
NOTES:
1. The BR0# pin is the only BREQ# signal that is bidirectional. The internal BREQ# signals are mapped onto BR# pins
after the agent ID is determined. See Section 7.0 for more information.
2. See Section 7.0 for information on the PWRGOOD signal.
3. See Section 7.0 for information on the SLP# signal.
4. See Section 7.0 for information on the THERMTRIP# signal.
5. These signals are specified for 2.5 V operation.
6. VCC
CORE is the power supply for the processor core.
VCC
L2
is the power supply for the L2 cache component core logic.
VID[4:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate VREF on the processor substrate.
VSS is system ground.
TESTHI should be connected to 2.5 V with a 100 k
resistor.
VCC
5 is not connected to the Pentium
III processor core. This supply is used for the test equipment and tools.
SLOTOCC# is described in Section 7.0.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
EMI pins are described in Section 7.0.
THERMDP, THERMDN are described in Section 7.0.
2.8.1
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK.
All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK.
Table 4.
System Bus Signal Groups
Group Name
Signals
AGTL+ Input
BPRI#, BR1#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#1,
D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input5
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2, SMI#,
SLP#3, STPCLK#
CMOS Output5
FERR#, IERR#, THERMTRIP#4
System Bus Clock
BCLK
APIC Clock
PICCLK
APIC I/O5
PICD[1:0]
TAP Input5
TCK, TDI, TMS, TRST#
TAP Output5
TDO
Power/Other6
VCC
CORE, VCCL2, VCC5, VID[4:0], VTT, VSS, SLOTOCC#, THERMDP, THERMDN,
BSEL[1:0], EMI, TESTHI, Reserved
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