参数资料
型号: BX80525U533512E
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, XMA
文件页数: 17/94页
文件大小: 898K
代理商: BX80525U533512E
Pentium
III Processor at 450 MHz, 500 MHz, 533B MHz, 550 MHz, 600/600B MHz
24
Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This specification applies to Pentium
III processors. For baseboard compatibility information on Pentium II
processors, refer to the Pentium
II Processor at 350, 400 and 450 MHz datasheet (Order Number 243657).
3. VccCORE and IccCORE supply the processor core and the TagRAM and BSRAM I/O buffers.
4. A variable voltage source should exist on all systems in the event that a different voltage is required. See Section 2.6 and
Table 1 for more information.
5. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to the
processor.
6. VTT must be held to 1.5 V ±9%. It is recommended that VTT be held to 1.5 V ±3% while the Pentium III processor
system bus is idle. This is measured at the processor edge fingers.
7. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the bottom side of the
baseboard. The requirements at the SC242 connector pins account for voltage drops (and impedance discontinuities)
across the connector, processor edge fingers, and to the processor core. VccCORE must return to within the static voltage
specification within 100
s after a transient event; see the VRM 8.2 DC-DC Converter Design Guidelines (Order
Number 243773) for further details.
8. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The requirements at
the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and
to the processor core. VccCORE must return to within the static voltage specification within 100 s after a transient
event.
9. VCCL2 and ICCL2 supply the second level cache. Unless otherwise noted, this specification applies to all Pentium III
processor cache sizes. Systems should be designed for these specifications, even if a smaller cache size is used.
10. Max ICC measurements are measured at VCC max voltage, 95
°C ±2 °C, under maximum signal loading conditions. The
Max Icc currents specified do not occur simultaneously under the stress measurement condition.
11. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at
maximum current output, is no greater than the nominal (i.e., typical) voltage level of VccCORE (VccCORE_TYP). In this
case, the maximum current level for the regulator, IccCORE_REG, can be reduced from the specified maximum current
IccCORE _MAX and is calculated by the equation:
IccCORE_REG = IccCORE_MAX × VccCORE_TYP / (VccCORE_TYP + VccCORE Tolerance, Transient)
12. The current specified is the current required for a single Pentium III processor. A similar amount of current is drawn
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is used (see
Section 2.1).
13. The current specified is also for AutoHALT state.
14. Maximum values are specified by design/characterization at nominal VccCORE and nominal V CCL2.
15. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance
tolerable and reaction time of the voltage regulator. This parameter is not tested.
16. dICC/dt specifications are measured and specified at the SC242 connector pins.
17. VCC5 and ICC5 are not used by the Pentium III processors. The VCC5 supply is used for the test equipment and tools.
IDSL
PL2
ICC Deep Sleep for
second level cache
0.1
A
2, 9, 10
dICC
CORE/dt
Power supply current
slew rate
20
A/s
2, 14, 15, 16
dICC
L2/dt
L2 cache power supply
current slew rate
1A/
s 14, 15, 16
dICCvTT/dt
Termination current slew
rate
8A/s
See
Table 10 14, 15
VCC5
5 V supply voltage
4.75
5.00
5.25
V
5 V ±5%
16, 17
ICC5
ICC for 5 V supply
voltage
1.0
A
17
Table 7.
Voltage and Current Specifications (Sheet 2 of 2)
Symbol
Parameter
Core Freq
Min
Typ
Max
Unit
Notes
1
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