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参数资料
| 型号： | BX80525U533512E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, MICROPROCESSOR, XMA |
| 文件页数： | 15/94页 |
| 文件大小： | 898K |
| 代理商： | BX80525U533512E |
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Pentium
III Processor at 450 MHz, 500 MHz, 533B MHz, 550 MHz, 600/600B MHz
22
Datasheet
2.10
Maximum Ratings
Table 6 contains Pentium III processor stress ratings only. Functional operation at the absolute
maximum and minimum is not implied nor guaranteed. The processor should not receive a clock
while subjected to these conditions. Functional operating conditions are given in the AC and DC
tables in Section 2.11 and Section 2.13. Extended exposure to the maximum ratings may affect
device reliability. Furthermore, although the processor contains protective circuitry to resist
damage from static electric discharge, one should always take precautions to avoid high static
voltages or electric fields.
NOTES:
1. Operating voltage is the voltage to which the component is designed to operate. See Table 7.
2. This rating applies to the VCC
CORE
, VCC
L2
, VCC
5, and any input (except as noted below) to the processor.
3. Parameter applies to CMOS, APIC, and TAP bus signal groups only.
4. The mechanical integrity of the latch arms is specified to last a maximum of 50 cycles.
5. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/extraction
cycles.
6. While insertion/extraction cycling above 50 insertions will cause an increase in the contact resistance (above 0.1
) and
a degradation in the material integrity of the edge finger gold plating, it is possible to have processor functionality above
the specified limit. The actual number of insertions before processor failure will vary based upon system configuration
and environmental conditions.
7. This specification only applies to S.E.C.C. packaged processors.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the Pentium III processor edge
fingers and at the SC242 connector pins. See Section 7.0 for the processor edge finger signal
definitions and Section 5.0 for the signal listing.
Most of the signals on the Pentium III processor system bus are in the AGTL+ signal group. These
signals are specified to be terminated to 1.5 V. The DC specifications for these signals are listed in
Table 8.
To allow connection with other devices, the Clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 9.
Table 6.
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TSTORAGE
Processor storage temperature
–40
85
°C
VCC
(All)
Any processor supply voltage
with respect to VSS
–0.5
Operating voltage + 1.0
V
1, 2
Vin
AGTL
AGTL+ buffer DC input
voltage with respect to VSS
–0.3
VCC
CORE + 0.7
V
Vin
CMOS
CMOS buffer DC input
voltage with respect to VSS
–0.3
3.3
V
3
IVID
Max VID pin current
5
mA
ISLOTOCC
Max SLOTOCC# pin current
5
mA
Mech Max
Latch Arms
Mechanical integrity of latch
arms
50
Cycles
4, 7
Mech Max Edge
Fingers
Mechanical integrity of
processor edge fingers
50
Insertions/
Extractions
5, 6
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