![](http://datasheet.mmic.net.cn/260000/C9811X2AYB_datasheet_15873003/C9811X2AYB_11.png)
Low EMI Clock Generator for Intel
810 Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 11 of 17
APPROVED PRODUCT
C9811x2
AC Parameters
66 MHz Host
Min
15.0
5.2
5.0
1.0
1.0
0.4
0.4
30.0
12.0
12.0
1.0
1.0
0.4
0.4
60.0
25.5
25.3
1.0
1.0
0.4
0.4
15.0
5.25
5.05
1.0
1.0
0.5
0.5
100 MHz Host
Min
10.0
3.0
2.8
1.0
1.0
0.4
0.4
30.0
12.0
12.0
1.0
1.0
0.4
0.4
60.00
25.5
25.3
1.0
1.0
0.4
0.4
15.0
5.25
5.05
1.0
1.0
0.5
0.5
Symbol
Parameter
Max
15.5
-
-
4.0
4.0
1.6
1.6
-
-
-
4.0
4.0
1.6
1.6
64.0
-
-
4.0
4.0
1.6
1.6
16.0
-
-
4.0
4.0
2.0
2.0
Max
10.5
-
-
4.0
4.0
1.6
1.6
-
-
-
4.0
4.0
1.6
1.6
64.0
-
-
4.0
4.0
1.6
1.6
16.0
-
-
4.0
4.0
2.0
2.0
Units
Notes
TPeriod
THigh
TLow
Edge Rate
Edge Rate
T Rise
T Fall
Tperiod
THigh
TLow
Edge Rate
Edge Rate
T Rise
T Fall
Tperiod
THigh
TLow
Edge Rate
Edge Rate
T Rise
T Fall
Tperiod
THigh
TLow
Edge Rate
Edge Rate
T Rise
T Fall
Host/CPU CLK period
Host/CPU CLK high time
Host/CPU CLK low time
Rising edge rate
Failing edge rate
Host/CPU CLK rise time
Host/CPU CLK fall time
IOAPIC 33 MHz CLK period
IOAPIC 33 MHz CLK high time
IOAPIC 33 MHz CLK low time
Rising edge rate
Failing edge rate
IOAPIC 33 MHz CLK rise time
IOAPIC 33 MHz CLK fall time
IOAPIC 16.67 MHz CLK period
IOAPIC 16.67 MHz CLK high time
IOAPIC 16.67 MHz CLK low time
Rising edge rate
Failing edge rate
IOAPIC 16.67 MHz CLK rise time
IOAPIC 16.67 MHz CLK fall time
3V66 CLK period
3V66 CLK high time
3V66 CLK low time
Rising edge rate
Failing edge rate
3V66 CLK rise time
3V66 CLK fall time
nS
nS
nS
V/nS
V/nS
nS
nS
nS
nS
nS
V/nS
V/nS
nS
nS
nS
nS
nS
V/nS
V/nS
nS
nS
nS
nS
nS
V/nS
V/nS
nS
nS
2,7
3
4
1
1
2,7
3
4
1
1
2,7
3
4
1
1
2,7
3
4
1
1