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参数资料
| 型号： | C9811X2AYB |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器| SSOP封装| 56PIN |塑料 |
| 文件页数： | 5/17页 |
| 文件大小： | 232K |
| 代理商： | C9811X2AYB |
Low EMI Clock Generator for Intel
810 Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 5 of 17
APPROVED PRODUCT
C9811x2
Power on Bi-Directional Pins
Power Up Condition:
Pin1 is a Power up bi-directional pin and is used for selecting the IOAPIC frequency in page 1, table 1. During power-up
of the device, this pin is in input mode (see Fig 4, below), therefore; it is
considered input select pins internal to the IC.
After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output. If
strapped low the IOAPIC clock is set to
of the PCI frequency (16.6 MHz). If strapped high IOAPIC is 33.3 MHz.
-
Hi-Z INPUTS
TOGGLE OUTPUTS
OWER SUPPLY
AMP
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL
Fig.4
REF / SEL2
(Pin 1)
VDD RAIL
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-
up each (250K
)
, therefore, a selection
“
1
”
is the
default. If the system uses a slow power supply (over
5mS settling time), then
it is recommended
to use an
external Pull-up (Rup) in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and B.
Fig. 5A represents an additional pull up resistor 50K
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection
“
0
”
is desired, then a jumper is placed on
JP1 to a 5K
resistor as implemented as shown in
Fig.5A. Please note the selection resistors (Rup and
Rdn
)
are placed before the Damping resistor (Rd)
close to the pin.
Fig. 5B represent a single resistor 10K
connected to a
3-way jumper, JP2. When a
“
1
”
selection is desired, a
jumper is placed between leads1 and 3. When a
“
0
”
selection is desired, a jumper is placed between leads 1
and 2.
Load
Load
Fig. 5A
Fig. 5B
Vdd
Vdd
Rup
10K
Rd
IMI C9811X2
Bidirectional
JP1
JUMPER
JP2
3 W ay Jum per
Rsel
10K
Rd
IMI C9811X2
Bidirectional
Rdn
10K
See Description
1
2
3
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