Low EMI Clock Generator for Intel
810 Chipset Systems
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07052 Rev. **
05/03/2001
Page 6 of 17
APPROVED PRODUCT
C9811x2
2-Wire SMBUS Control Interface
The 2-wire control interface implements a write slave only interface according to SMBus specification. (See Fig. 7 / P. 8).
Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The
2-wire control interface allows each clock output to be individually enabled or disabled. 100 Kbits/second (standard
mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is an 8-bit address. W#=0 in write mode.
The device will respond to writes to 10 bytes (max) of data to address
D2
by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. The device
will not respond to any other control interface conditions, and previously set control registers are retained.
SMBUS Test Circuitry
Fig.6
Note: Buffer is 7407 with VCC @ 5.0 V
2.2 K
Device under Test
SDATA
DATAIN
SCLK
DATAOUT
CLOCK
+ 5V
+ 5V
+ 5V
2.2 K
2.2 K