参数资料
型号: CDK5571
厂商: Cirrus Logic Inc
文件页数: 14/34页
文件大小: 0K
描述: CDB5571 W/CAPTURE PLUS 2 SYSTEM
标准包装: 1
系列: CapturePLUS™II
ADC 的数量: 1
位数: 16
采样率(每秒): 100k
数据接口: 串行
输入范围: 2.4 ~ 4.2 V
工作温度: -40°C ~ 85°C
已用 IC / 零件: CS5571
已供物品: 2 个板,线缆,CD,电源
产品目录页面: 756 (CN2011-ZH PDF)
相关产品: CS5571-ISZR-ND - IC ADC 16BIT DELTA-SIGMA 24-SSOP
598-1266-5-ND - IC ADC 16BIT 1CH 100KSPS 24SSOP
其它名称: 598-1279
CDK5571-1
3/25/08
10:56
CS5571
Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are
emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two
MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data
is put into the port register.
See Serial Port on page 26 for information about reading conversion data.
Conversion performance can be affected by several factors. These include the choice of clock source for
the chip, the timing of CONV, the setting of the DITHER function, and the choice of the serial port mode.
The converter can be operated from an internal oscillator. This clock source has greater jitter than an
external crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-fre-
quency AC signals, but can become an issue for higher frequency AC signals. For maximum performance
when digitizing AC signals, a low-jitter MCLK should be used.
To achieve the highest resolution when measuring a DC signal with a single conversion the DITHER func-
tion should be off. If averaging is to be performed with multiple conversions of a DC signal, DITHER
should be on. To maximize performance, the CONV pin should be held low in the continuous conversion
state to perform multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK
falls.
If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause in-
terference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interfer-
ence due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a
conversion is not in progress.
3.2 Clock
The CS5571 can be operated from its internal oscillator or from an external master clock. The state of
MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and
be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK,
the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held
high, the internal oscillator will be held in the stopped state. The MCLK input can be held high to delete
clock cycles to aid in synchronizing multiple converters in different phase relationships.
The internal oscillator can be used if the signals to be measured are essentially DC. The internal oscillator
exhibits jitter at about 500 picoseconds rms. If the CS5571 is used to digitize AC signals, an external
low-jitter clock source should be used.
If the internal oscillator is used as the clock for the CS5571, the maximum conversion rate will be dictated
by the oscillator frequency.
If driven from an external MCLK source, the fast rise and fall times of the MCLK signal can result in clock
coupling from the internal bond wire of the IC to the analog input. Adding a 50 ohm resistor on the external
MCLK source significantly reduces this effect.
14
DS768PP1
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相关代理商/技术参数
参数描述
CDK5571-1 制造商:Cirrus Logic 功能描述:- Bulk
CDK5571-1/FAE 制造商:Cirrus Logic 功能描述:- Bulk
CDK5571-2 功能描述:CDB5570-2 W/CAPTURE PLUS 2 SYSTM RoHS:是 类别:编程器,开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 类型:MCU 适用于相关产品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、缆线、软件、数据表和用户手册 其它名称:520-1035
CDK5580 功能描述:数据转换 IC 开发工具 KIT CDB558 w/ Capture Plus II RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V
CDK5581 功能描述:数据转换 IC 开发工具 KIT CDB558 w/ Capture Plus II RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V