参数资料
型号: CDK5571
厂商: Cirrus Logic Inc
文件页数: 27/34页
文件大小: 0K
描述: CDB5571 W/CAPTURE PLUS 2 SYSTEM
标准包装: 1
系列: CapturePLUS™II
ADC 的数量: 1
位数: 16
采样率(每秒): 100k
数据接口: 串行
输入范围: 2.4 ~ 4.2 V
工作温度: -40°C ~ 85°C
已用 IC / 零件: CS5571
已供物品: 2 个板,线缆,CD,电源
产品目录页面: 756 (CN2011-ZH PDF)
相关产品: CS5571-ISZR-ND - IC ADC 16BIT DELTA-SIGMA 24-SSOP
598-1266-5-ND - IC ADC 16BIT 1CH 100KSPS 24SSOP
其它名称: 598-1279
CDK5571-1
3/25/08
10:56
CS5571
3.13 Using the CS5571 in Multiplexing Applications
The CS5571 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to
achieve high signal-to-noise performance. This means that once a conversion is started, the converter
takes many samples to compute the resulting output word. The analog input for the signal to be converted
must remain active during the entire conversion until RDY falls.
The CS5571 can be used in multiplexing applications, but the system timing for changing the multiplexer
channel and for starting a new conversion will depend upon the multiplexer system architecture.
The simplest system is illustrated in Figure 27 . Any time the multiplexer is changed, the analog signal
presented to the converter must fully settle. After the signal has settled, the CONV signal is issued to the
converter to start a conversion. Being a delta-sigma converter, the signal must remain present at the input
of the converter until the conversion is completed. Once the conversion is completed, RDY falls. At this
time the multiplexer can be changed to the next channel and the data can be read from the serial port.
The CONV signal should be delayed until after the data is read and until the new analog signal has settled.
In this configuration, the throughput of the converter will be dictated by the settling time of the analog input
circuit and the conversion time of the converter. The conversion data can be read from the serial port after
the multiplexer is changed to the new channel while the analog input signal is settling.
CS5571
CH1
CH2
CH3
CH4
90
150pF
2k
4700pF
C0G
AIN
ACOM
Amplifier
Amplifier
CONV
RDY
Settling Time
Conversion Time
Settling Time
Advance
Mux
CH1
Throughput
CH2
Figure 27. Simple Multiplexing Scheme
A more complex multiplexing scheme can be used to increase the throughput of the converter is illustrated
in Figure 28 . In this circuit, two banks of multiplexers are used.
DS768PP1
27
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