参数资料
型号: CDK5571
厂商: Cirrus Logic Inc
文件页数: 20/34页
文件大小: 0K
描述: CDB5571 W/CAPTURE PLUS 2 SYSTEM
标准包装: 1
系列: CapturePLUS™II
ADC 的数量: 1
位数: 16
采样率(每秒): 100k
数据接口: 串行
输入范围: 2.4 ~ 4.2 V
工作温度: -40°C ~ 85°C
已用 IC / 零件: CS5571
已供物品: 2 个板,线缆,CD,电源
产品目录页面: 756 (CN2011-ZH PDF)
相关产品: CS5571-ISZR-ND - IC ADC 16BIT DELTA-SIGMA 24-SSOP
598-1266-5-ND - IC ADC 16BIT 1CH 100KSPS 24SSOP
其它名称: 598-1279
CDK5571-1
3/25/08
10:56
CS5571
3.7 AIN & VREF Sampling Structures
The CS5571 uses on-chip buffers on the AIN and VREF+ inputs. Buffers provide much higher input im-
pedance and therefore reduce the amount of drive current required from an external source. This helps
minimize errors.
The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is
connected to the V1+ supply, the buffers will be enabled. If the BUFEN pin is connected to the V1- pin,
the buffers are off. The converter will consume about 30 mW less power when the buffers are off, but the
input impedances of AIN, ACOM and VREF+ will be significantly less than with the buffers enabled.
3.8 Converter Performance
The CS5571 achieves excellent differential nonlinearity (DNL) as shown in figures 9 and 10. Figure 9 il-
lustrates the code widths on a typical scale of ±1 LSB. Figure 10 illustrates a zoom view of figure 9 on a
scale of ±0.1 LSB. Figure 10 also includes a DNL error histogram that indicates that the errors are equally
distributed about the perfect code size; and most codes are accurate within ±0.01 LSB.
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
1
Codes
65535
Figure 9. CS5571 DNL Plot
+0.10
+0.08
+0.06
+0.04
+0.02
0
-0.02
-0.04
-0.06
-0.08
+0.1
+0.09
+0.08
+0.07
+0.06
+0.05
+0.04
+0.03
+0.02
+0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.10
1
65535
18k
16k
14k
12k
10k
8k
6k
4k
2k
0
-0.1
Codes
Counts per 0.01 LSB Error
Figure 10. CS5581 DNL Error Plot with DNL Histogram
20
DS768PP1
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相关代理商/技术参数
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CDK5571-1 制造商:Cirrus Logic 功能描述:- Bulk
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