参数资料
型号: CDK5571
厂商: Cirrus Logic Inc
文件页数: 6/34页
文件大小: 0K
描述: CDB5571 W/CAPTURE PLUS 2 SYSTEM
标准包装: 1
系列: CapturePLUS™II
ADC 的数量: 1
位数: 16
采样率(每秒): 100k
数据接口: 串行
输入范围: 2.4 ~ 4.2 V
工作温度: -40°C ~ 85°C
已用 IC / 零件: CS5571
已供物品: 2 个板,线缆,CD,电源
产品目录页面: 756 (CN2011-ZH PDF)
相关产品: CS5571-ISZR-ND - IC ADC 16BIT DELTA-SIGMA 24-SSOP
598-1266-5-ND - IC ADC 16BIT 1CH 100KSPS 24SSOP
其它名称: 598-1279
CDK5571-1
3/25/08
10:56
SWITCHING CHARACTERISTICS
T A = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
CS5571
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
Master Clock Duty Cycle
Internal Oscillator
External Clock
XIN
f clk
12
0.5
40
14
16
-
16
16.2
60
MHz
MHz
%
Reset
RST Low Time
RST rising to RDY falling
(Note 9)
Internal Oscillator
External Clock
t res
t wup
1
-
-
-
120
1536
-
-
-
μs
μs
MCLKs
Conversion
CONV Pulse Width
t cpw
4
-
-
MCLKs
BP/UP setup to CONV falling
t scn
0
-
-
ns
CONV low to start of conversion
Perform Single Conversion (CONV high before RDY falling)
t scn
t bus
-
20
-
-
2
-
MCLKs
MCLKs
Conversion Time
Start of Conversion to RDY falling
t buh
-
-
164
MCLKs
6
9.
10.
11.
Reset must not be released until the power supplies and the voltage reference are within specification.
BP/UP can be changed coincident to CONV falling. BP/UP must remain stable until RDY falls.
If CONV is held low continuously, conversions occur every 160 MCLK cycles.
If RDY is tied to CONV, conversions will occur every 162 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 164 MCLKs.
RDY falls at the end of conversion.
DS768PP1
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