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| 型号： | COP8CDR9HVA8/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 64/111页 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 8BIT 44-PLCC |
| 标准包装： | 25 |
| 系列： | COP8™ 8C |
| 核心处理器： | COP8 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | Microwire/Plus（SPI），UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 37 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
| 其它名称： | *COP8CDR9HVA8 *COP8CDR9HVA8/NOPB COP8CDR9HVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.12.5.1.1 Entering The Low Speed Halt Mode
The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1.
All processor action stops in the middle of the next instruction cycle, and power consumption is reduced to
a very low level. In order to expedite exit from HALT, the low speed oscillator is left running when the
device is Halted in the Low Speed mode. However, the Idle Timer will not be clocked.
5.12.5.1.2 Exiting The Low Speed Halt Mode
When the HALT mode is entered by setting bit 7 of the Port G data register, there is a choice of methods
for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input Wake-up. The Reset
method and Multi-Input Wake-up method can be used with any clock option, but the availability of the G7
input is dependent on the clock option.
5.12.5.1.3 HALT Exit Using Reset
A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the
Low Speed mode and puts it into the High Speed mode.
5.12.5.1.4 HALT Exit Using Multi-Input Wake-up
The device can be brought out of the HALT mode by a transition received on one of the available Wake-
up pins. The pins used and the types of transitions sensed on the Multi-input pins are software
programmable. For information on programming and using the Multi-Input Wake-up feature, refer to the
Multi-Input Wake-up section.
As the low speed oscillator is left running, there is no start up delay when exiting the low speed halt mode,
regardless of the state of the CLKDLY bit.
NOTE
To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the
instruction in the application program used for entering the HALT mode should be followed
by two consecutive NOP (no-operation) instructions.
5.12.5.1.5 Options
This device has two options associated with the HALT mode. The first option enables the HALT mode
feature, while the second option disables HALT mode operation. Selecting the disable HALT mode option
will cause the microcontroller to ignore any attempts to HALT the device under software control. See the
Option section for more details on this option bit.
5.12.5.2 Low Speed Idle Mode
In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with
the HALT mode. However, the low speed oscillator, IDLE Timer (Timer T0), and Clock Monitor continue to
operate, allowing real time to be maintained. The device remains idle for a selected amount of time up to 2
seconds, and then automatically exits the IDLE mode and returns to normal program execution using the
low speed clock.
The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G
data register).
The IDLE Timer window is selectable from one of five values, 0.125 seconds, 0.25 seconds, 0.5 seconds,
1 second, and 2 seconds. Selection of this value is made through the ITMR register.
56
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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