- 您现在的位置：买卖IC网 > PDF目录10936 > COP8CDR9HVA8/NOPB (National Semiconductor)IC MCU CMOS 8BIT 44-PLCC PDF资料下载
参数资料
| 型号： | COP8CDR9HVA8/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 85/111页 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 8BIT 44-PLCC |
| 标准包装： | 25 |
| 系列： | COP8™ 8C |
| 核心处理器： | COP8 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | Microwire/Plus（SPI），UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 37 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
| 其它名称： | *COP8CDR9HVA8 *COP8CDR9HVA8/NOPB COP8CDR9HVA8 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页当前第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable
interrupt condition cannot trigger an interrupt until the program enables it by setting both the GIE bit and
the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously
activated (set) pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous
occurrences of the interrupt should be ignored, the associated pending bit must be reset to zero prior to
enabling the interrupt. Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it
will immediately trigger an interrupt. A maskable interrupt is active if its associated enable and pending
bits are set.
An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any
interrupt which occurs during the execution of an instruction is not acknowledged until the start of the next
normally executed instruction. If the next normally executed instruction is to be skipped, the skip is
performed before the pending interrupt is acknowledged.
At the start of interrupt acknowledgment, the following actions occur:
1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from
interrupting the current service routine. This feature prevents one maskable interrupt from interrupting
another one being serviced.
2. The address of the instruction about to be executed is pushed onto the stack.
3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location.
The device requires seven instruction cycles to perform the actions listed above.
If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by
writing to the PSW register, and thus allow other maskable interrupts to interrupt the current service
routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in
such a way as to prevent stack overflow, loss of saved context information, and other unwanted
conditions.
The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the
cause of the interrupt, and jump to the interrupt handling routine corresponding to the highest priority
enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits
to determine the source(s) of the interrupt. If more than one interrupt is active, the user's program must
decide which interrupt to service.
Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically
done as early as possible in the service routine in order to avoid missing the next occurrence of the same
type of interrupt event. Thus, if the same event occurs a second time, even while the first occurrence is
still being serviced, the second occurrence will be serviced immediately upon return from the current
interrupt routine.
An interrupt service routine typically ends with an RETI instruction. This instruction set the GIE bit back to
1, pops the address stored on the stack, and restores that address to the program counter. Program
execution then proceeds with the next instruction that would have been executed had there been no
interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately
upon return from the previous interrupt.
NOTE
While executing from the Boot ROM for ISP or virtual E2 operations, the hardware will
disable interrupts from occurring. The hardware will leave the GIE bit in its current state, and
if set, the hardware interrupts will occur when execution is returned to Flash Memory.
Subsequent interrupts, during ISP operation, from the same interrupt source will be lost.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
75
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J63-IX-S | CONVERTER MOD DC/DC 24V 75W |
| VI-J62-IX-S | CONVERTER MOD DC/DC 15V 75W |
| VI-J4X-IX-S | CONVERTER MOD DC/DC 5.2V 75W |
| VI-J40-IX-S | CONVERTER MOD DC/DC 5V 75W |
| VE-JNF-IX-S | CONVERTER MOD DC/DC 72V 75W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| COP8CDR9IMT7 | 制造商:Rochester Electronics LLC 功能描述:32K FLASH, 10 BIT A/D, NO BO - Bulk |
| COP8CDR9IMT8 | 功能描述:IC MCU CMOS 8BIT 48-TSSOP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:COP8™ 8C 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
| COP8CDR9IMTA8 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout |
| COP8CDR9KMT7 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 32k Memory, Virtual EEPROM, 10-Bit A/D and Brownout |
| COP8CDR9KMT8 | 功能描述:IC MCU EEPROM 8BIT 32K 56-TSSOP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:COP8™ 8C 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
发布紧急采购，3分钟左右您将得到回复。