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| 型号： | COP8CDR9HVA8/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 71/111页 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 8BIT 44-PLCC |
| 标准包装： | 25 |
| 系列： | COP8™ 8C |
| 核心处理器： | COP8 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | Microwire/Plus（SPI），UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 37 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
| 其它名称： | *COP8CDR9HVA8 *COP8CDR9HVA8/NOPB COP8CDR9HVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.13.3 ASSOCIATED I/O PINS
Data is transmitted on the TDX pin and received on the RDX pin. TDX is the alternate function assigned to
Port L pin L2; it is selected by setting ETDX (in the ENUI register) to one. RDX is an inherent function Port
L pin L3, requiring no setup. Port L pin L2 must be configured as an output in the Port L Configuration
Register in order to be used as the TDX pin.
The baud rate clock for the USART can be generated on-chip, or can be taken from an external source.
Port L pin L1 (CKX) is the external clock I/O pin. The CKX pin can be either an input or an output, as
determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a clock signal which
may be selected to drive the transmitter and/or receiver. As an output, it presents the internal Baud Rate
Generator output.
NOTE
The CKX pin is unavailable if Port L1 is used for the Low Speed Oscillator.
5.13.4 USART OPERATION
The USART has two modes of operation: asynchronous mode and synchronous mode.
5.13.4.1 Asynchronous Mode
This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to the
USART is 16 times the baud rate.
The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current
character on the TDX pin, the TBUF register may be loaded by software with the next byte to be
transmitted. When TSFT finishes transmitting the current character the contents of TBUF are transferred
to the TSFT register and the Transmit Buffer Empty Flag (TBMT in the ENU register) is set. The TBMT
flag is automatically reset by the USART when software loads a new character into the TBUF register.
There is also the XMTG bit which is set to indicate that the USART is transmitting. This bit gets reset at
the end of the last frame (end of last Stop bit). TBUF is a read/write register.
The RSFT and RBUF registers double-buffer data being received. The USART receiver continually
monitors the signal on the RDX pin for a low level to detect the beginning of a Start bit. Upon sensing this
low level, it waits for half a bit time and samples again. If the RDX pin is still low, the receiver considers
this to be a valid Start bit, and the remaining bits in the character frame are each sampled a three times
around the center of the bit time. Serial data input on the RDX pin is shifted into the RSFT register. Upon
receiving the complete character, the contents of the RSFT register are copied into the RBUF register and
the Received Buffer Full Flag (RBFL) is set. RBFL is automatically reset when software reads the
character from the RBUF register. RBUF is a read only register. There is also the RCVG bit which is set
high when a framing error or a break detect occurs and goes low once RDX goes high.
5.13.4.2 Synchronous Mode
In this mode data is transferred synchronously with the clock. Data is transmitted on the rising edge and
received on the falling edge of the synchronous clock.
This mode is selected by setting SSEL bit in the ENUI register. The input frequency to the USART is the
same as the baud rate.
When an external clock input is selected at the CKX pin, data transmit and receive are performed
synchronously with this clock through TDX/RDX pins.
If data transmit and receive are selected with the CKX pin as clock output, the device generates the
synchronous clock output at the CKX pin. The internal baud rate generator is used to produce the
synchronous clock. Data transmit and receive are performed synchronously with this clock.
62
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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