参数资料
型号: CORE1553-SA
厂商: Microsemi SoC
文件页数: 1/30页
文件大小: 0K
描述: HARDWARE FOR IP CORE1553
标准包装: 1
类型: FPGA
适用于相关产品: Core1553
所含物品:
Core1553BBC MIL-STD-1553B Bus Controller
Product Summary
?
– Synthesis Scripts
Actel-Developed Testbenches, VHDL and Verilog
Intended Use
? 1553B Bus Controller (BC)
? DMA Backend Interface to External Memory
Synthesis and Simulation Support
? Synthesis: Synplicity ? , Synopsys ? (Design Compiler ? /
FPGA Compiler TM /FPGA Express TM ), Exemplar TM
Key Features
? Supports MIL-STD-1553B
?
Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
?
Interfaces to External RAM
– Supports up to 128kbytes of Memory
Verification and Compliance
– Synchronous or Asynchronous Backend
Interface
– Backend Interface Identical to Core1553BRT
?
?
Actel-Developed Simulation Testbench
Core Implemented on the 1553B BC Development
System
?
?
?
Selectable Clock Rate of 12, 16, 20, or 24 MHz
Provides Direct CPU Access to Memory
Interfaces to Standard 1553B Transceivers
?
Third-Party 1553B Compliance Testing of the
1553B Encoder and Decoder Blocks Implemented
in an A54SXA32-STD Device
?
Fully Automated Message Scheduling
– Frame Support
Development System (Optional)
– Conditional Branching and Sub-routines
– Variable Inter-message Gaps and RT Response
Times
?
?
Complete 1553B BC Implementation in an SX-A
Device
Includes a PCI Interface for Host CPU Connection
– Real Time Clock for Message Scheduling
?
Includes Transceivers
and
Bus
Termination
– Asynchronous Message Support
Supported Families
Components
Contents
?
Fusion
?
?
?
?
?
?
ProASIC3/E
ProASIC PLUS
Axcelerator
RTAX
SX-A
RTSX-S
Core Deliverables
?
Netlist Version
Compiled RTL Simulation Model, Compliant
with the Actel Libero? Integrated Design
Environment (IDE)
– Compatible with the Actel Designer Place-and-
Route Tool
?
RTL Version
– VHDL or Verilog Core Source Code
December 2005
? 2005 Actel Corporation
v 4 .0
1
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