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参数资料
| 型号： | CORE1553-SA |
| 厂商： | Microsemi SoC |
| 文件页数： | 14/30页 |
| 文件大小： | 0K |
| 描述： | HARDWARE FOR IP CORE1553 |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Core1553 |
| 所含物品： | 板 |
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Core1553BBC MIL-STD-1553B Bus Controller
Table 14 ? Supported Instructions (Continued)
OPCODE Function Condition Code Parameter
Description
0110
0111
1000
LOADC
WAITC
CALL
Yes
Yes
Yes
Clock value
Clock value
New Instruction Address
Loads the BC clock
Waits until the BC clock reaches the specified value
Jumps to the new message list address and pushes the return
address onto the stack
1001
1010
RET
RETAS
Yes
Yes
N/A
N/A
Gets a return instruction address from the stack and jumps to it
Gets a return instruction address from the stack and jumps to
it. Also clears the ASYNC bit in the status register allowing
further ASYNC messages to be accepted.
1011
STOREF
Yes
N/A
Stores the selected flag so that it may be tested at a later stage.
The condition code field indicates which flag to store.
Others
Illegal
N/A
N/A
Will halt operation and set the illegal OPCODE interrupt
Table 15 ? Condition Codes
Condition Code Function Description
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
10000
10001
10010
10011
10100
10101
10110
14
ALWAYS
RESP
GBR
TF
DBA
SSF
BUSY
BR
SR
ME
SWE
SWAB
ASYNC
EXT
SFLAG
NEVER
NORESP
NGBR
NTF
NDBA
NSSF
NBUSY
Always perform the associated instruction
Performs the instruction if there was a response to the previous message
Performs the instruction if the previous message was successful
Performs the instruction if the Terminal Flag was set in the last received status word
Perform the instruction if the Dynamic Bus Acceptance flag was set in the last received status word
Performs the instruction if the Sub-system Flag was set in the last received status word
Performs the instruction if the Busy bit was set in the last received status word
Performs the instruction if the Broadcast Received bit was set in the last received status word
Performs the instruction if the Service Request bit was set in the last received status word
Performs the instruction if the Message Error bit was set in the last received status word
Performs the instruction if the RT address field is incorrect, the instrumentation bit is set, or any of the
reserved bits was set in the last received status word
Performs the instruction if any bits are set in the last received status word (ignoring the RT address
field)
Performs the instruction if asynchronous message processing is active
Performs the instruction if the External flag input is active '1'
Performs the instruction if the previously stored flag bit was set
Never performs the associated instruction
Performs the instruction if there was no response to the previous message
Performs the instruction if the previous message was unsuccessful
Performs the instruction if the Terminal Flag was not set in the last received status word
Performs the instruction if the Dynamic Bus Acceptance flag was not set in the last received status
word
Performs the instruction if the Sub-System Flag was not set in the last received status word
Performs the instruction if the Busy bit was not set in the last received status word
v4.0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CORE16550-AN | 制造商:Microsemi Corporation 功能描述:CORE16X50 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER - Virtual or Non-Physical Inventory (Software & Literature) |
| CORE16550-AR | 制造商:Microsemi Corporation 功能描述:CORE16X50 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER - Virtual or Non-Physical Inventory (Software & Literature) |
| CORE16550-RM | 制造商:Microsemi Corporation 功能描述:CORE - Virtual or Non-Physical Inventory (Software & Literature) |
| CORE429-AN | 功能描述:IP MODULE CORE429 RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| CORE429-AR | 功能描述:IP MODULE CORE429 RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
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