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| 型号： | CORE1553-SA |
| 厂商： | Microsemi SoC |
| 文件页数： | 19/30页 |
| 文件大小： | 0K |
| 描述： | HARDWARE FOR IP CORE1553 |
| 标准包装： | 1 |
| 类型： | FPGA |
| 适用于相关产品： | Core1553 |
| 所含物品： | 板 |
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Core1553BBC MIL-STD-1553B Bus Controller
Error Conditions
Core1553BBC monitors bus errors and in most cases will perform automatic retry operations if recovery is possible
Table 18 ? Error Conditions
Error Condition
Group
Signaling
Error
1553B signaling error, parity, Manchester error, too Message is retried
Action
many or to few words, or incorrect SYNC type
1553B Loopback Failure. Can occur if an RT responds Message is retried
late, causing the RT response and following command Loopback bit set in BC status
word to corrupt each other on the bus
BC continues to process messages
Transmitter Overrun. Internal timer detects the BC has BC controller aborts and asserts the transmitter
transmitted for greater than 688 μ s.
shutdown interrupt
Memory
Status Word
RT Response
Miscellaneous
Retry Fails
Memory Access Failure
Stack Overflow or Underflow
Terminal Flag in SW
Sub-system Flag in SW
Service Request Flag in SW
Broadcast bit is SW
Busy Flag in SW
Message Error bit in SW
Other SW bit
No or Late Response
Corrupt Instruction List
Illegal OPCODE
Message block MSGCMD message type bits [3:0]
mismatch the provided command word
Retries do not correct the error
BC controller aborts and asserts the memory failure
interrupt
BC controller aborts and asserts the stack overflow
interrupt
Unexpected bit in 1553B status bit set in the TSW.
Message is not retried.
Message is retried
Message is retried
Message is retried
BC controller aborts and asserts the corrupt instruction
list interrupt.
Message Okay bit in TSW not set
CPU Interface
Start or second asynchronous message command issued Command is ignored and an illegal command interrupt
while an asynchronous message is active
Loop Back Tests
The Core1553BBC performs loopback testing on all of its
transmissions; the transmit data is fed back into the
receiver and each transmitted word is compared to the
original. If an error is detected, the transmitter
shutdown bit is set in the BC status register.
Message Sequence Control
Core1553BBC message sequence control enables it to
automatically sequence messages without CPU
intervention. It supports conditional jumps and sub-
routine calls as well as time control functions.
v4.0
is generated.
All instructions make use of the condition codes. The
condition codes cover error conditions, 1553B status
word values, and an external input. Core1553BBC
supports CALL and RETURN instructions with the aid of a
stack that allows for 255 return addresses to be stored.
The stack occupies the top 256 words of memory.
To support message timing and minor/major frame
timing, Core1553BBC has a built-in real-time clock (16-
bit) and timer (8-bit) that can be used to synchronize
message timing. The real time clock and timer have a
programmable resolution of 1 μ s, 4 μ s, 8 μ s, or 32 μ s.
Messages can be programmed to be sent at an absolute
time or relative to the end of the previous message.
19
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