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| 型号： | CRD5463PM-Z |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 16/46页 |
| 文件大小： | 0K |
| 描述： | REFERENCE DESIGN FOR POWER METER |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5463 |
| 主要属性： | 单相功率表 |
| 次要属性： | 90 ~ 260 VAC |
| 已供物品： | 模块，适配器，线缆，电源线 |
| 其它名称： | 598-1943 |
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CS5463
5. FUNCTIONAL DESCRIPTION
250mV P
--------------------- ? 176.78mV
2
? MCLK ? K ?
5.1 Analog Inputs
The CS5463 is equipped with two fully differential input
channels. The inputs VIN ? and IIN ? are designated as
the voltage and current channel inputs, respectively.
The full-scale differential input voltage for the current
and voltage channel is ? 250 mV P .
5.1.1 Voltage Channel
The output of the line voltage resistive divider or trans-
former is connected to the VIN+ and VIN- input pins of
the CS5463. The voltage channel is equipped with a
10x fixed-gain amplifier. The full-scale signal level that
can be applied to the voltage channel is ? 250 mV. If the
input signal is a sine wave the maximum RMS voltage
at a gain 10x is:
RMS
which is approximately 70.7% of maximum peak volt-
age. The voltage channel is also equipped with a Volt-
age Gain Register , allowing for an additional
programmable gain of up to 4x.
5.1.2 Current Channel
The output of the current-sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5463. To accommodate different current sensing el-
ements the current channel incorporates a programma-
ble gain amplifier (PGA) with two programmable input
gains. Configuration Register bit Igain (see Table 1) de-
fines the two gain selections and corresponding maxi-
mum input-signal level.
applied to the voltage and/or current channel, the maxi-
mum input range should be adjusted accordingly.
5.2 IIR Filters
The current and voltage channel are equipped with a
4th-order IIR filter, that is used to compensate for the
magnitude roll off of the low-pass decimation filter. Op-
erational Mode Register bit IIR engages the IIR filters in
both the voltage and current channels.
5.3 High-pass Filters
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both chan-
nels, no error component will be generated at DC when
computing V RMS , I RMS , and apparent power. Operation-
al Mode Register bits VHPF and IHPF activate the HPF
in the voltage and current channel respectively. When a
high-pass filter is active in only one channel, an all-pass
filter (APF) is applied to the other channel. The APF has
an amplitude response that is flat within the channel
bandwidth and is used for matching phase in systems
where only one HPF is engaged.
5.4 Performing Measurements
The CS5463 performs measurements of instantaneous
voltage (V n ) and current (I n ), and calculates instanta-
neous power (P n ) at an output word rate (OWR) of
OWR = -----------------------------
1024
where K is the clock divider selected in the Configura-
tion Register .
Igain
Maximum Input Range
The RMS voltage (V RMS ), RMS current (I RMS ), and ac-
0
±250 mV
10x
tive power (P active ) are computed using N instantaneous
Computation Cycle = ---------------
1 ±50 mV 50x
Table 1. Current Channel PGA Setting
For example, if Igain=0, the current channel’s PGA gain
is set to 10x. If the input signals are pure sinusoids with
zero phase shift, the maximum peak differential signal
on the current or voltage channel is ? 250 mV P . The in-
put signal levels are approximately 70.7% of maximum
peak voltage producing a full-scale energy pulse regis-
tration equal to 50% of absolute maximum energy pulse
registration. This will be discussed further in See Sec-
tion 5.5 Energy Pulse Output on page 17.
The Current Gain Register also facilitates an additional
programmable gain of up to 4x. If an additional gain is
16
samples of V n , I n , and P n respectively, where N is the
value in the Cycle Count Register and is referred to as
a “ computation cycle ”. The apparent power (S) is the
product of V RMS and I RMS . A computation cycle is de-
rived from the master clock (MCLK), with frequency:
OWR
N
Under default conditions and with K = 1, N = 4000, and
MCLK = 4.096 MHz – the OWR = 4000 Hz and the
Computation Cycle = 1 Hz.
All measurements are available as a percentage of full
scale. The format for signed registers is a two’s comple-
ment, normalized value between -1 and +1. The format
DS678F3
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