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| 型号： | CRD5463PM-Z |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 17/46页 |
| 文件大小： | 0K |
| 描述： | REFERENCE DESIGN FOR POWER METER |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5463 |
| 主要属性： | 单相功率表 |
| 次要属性： | 90 ~ 260 VAC |
| 已供物品： | 模块，适配器，线缆，电源线 |
| 其它名称： | 598-1943 |
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CS5463
for unsigned registers is a normalized value between 0
and 1. A register value of
the pulse output mode, which is controlled by bit
E2MODE in the Operational Mode Register.
? 2
– 1 ?
23
------------------------ = 0.99999988
23
2
E2MODE
0
1
E2 Output Mode
Sign of Energy
Apparent Energy
represents the maximum possible value.
At each instantaneous measurement, the CRDY bit will
be set in the Status Register , and the INT pin will be-
come active if the CRDY bit is unmasked in the Mask
Register . At the end of each computation cycle, the
DRDY bit will be set in the Status Register , and the INT
pin will become active if the DRDY bit is unmasked in
Table 2. E2 Pin Configuration
The E3 pin can be set to register Reactive Energy (de-
fault), PFMON, Voltage Channel Sign, or Apparent En-
ergy. Table 3 defines the pulse output format, which is
controlled by bits E3MODE[1:0] in the Operational
Mode Register.
the Mask Register . When these bits are asserted, they
must be cleared before they can be asserted again.
If the Cycle Count Register (N) is set to 1, all output cal-
culations are instantaneous, and DRDY, like CRDY, will
indicate when instantaneous measurements are fin-
ished. Some calculations are inhibited when the cycle
E3MODE1
0
0
1
1
E3MODE0
0
1
0
1
E3 OutPut Mode
Reactive Energy
PFMON
Voltage Channel Sign
Apparent Energy
count is less than 2.
Epsilon ( ? ) is the ratio of the input line frequency (f i ) to
the sample frequency (f s ) of the ADC.
Table 3. E3 Pin Configuration
The pulse output frequency of E1, E2, and E3 is directly
proportional to the power calculated from the input sig-
?
= f i ? f s
nals. The value contained in the PulseRateE Register is
the ratio of the frequency of energy-output pulses to the
where f s = MCLK / (K*1024). With MCLK = 4.096 MHz
and clock divider K = 1, f s = 4000 Hz. For the two
most-common line frequencies, 50 Hz and 60 Hz
number of samples, at full scale, which defines the av-
erage frequency for the output pulses. The pulse width,
t pw in Figure 2, is programmable through the Pulse-
Width register, and is approximately equal to:
t pw ? sec ? ? PulseWidth ? ------------------------------------------------
and
?
?
= 50 Hz ? 4000 Hz = 0.0125
= 60 Hz ? 4000 Hz = 0.015
1
( MCLK/K ) / 1024
If MCLK = 4.096 MHz, K = 1, and PulseWidth = 1, then
t pw ? 0.25 ms.
respectively. Epsilon is used to set the frequency of the
internal sine/cosine reference for the fundamental ac-
tive and reactive measurements, and the gain of the 90°
phase shift (IIR) filter for the average reactive power.
5.5 Energy Pulse Output
The CS5463 provides three output pins for energy reg-
istration. By default, E1 registers active energy, E3 reg-
isters reactive energy, and E2 indicates the sign of both
active and reactive energy. (See Figure 2. Timing Dia-
gram for E1, E2, and E3 on page13.) The E1 pulse out-
put is designed to register the Active Energy. The E2 pin
can be set to register Apparent Energy. Table 2 defines
DS678F3
5.5.1 Active Energy
The E1 pin produces active-low pulses with an output
frequency proportional to the active power. The E2 pin
is the energy direction indicator. Positive energy is rep-
resented by E1 pin falling while the E2 is high. Negative
energy is represented by the E1 pin falling while the E2
is low. The E1 and E2 switching characteristics are
specified in Figure 2. Timing Diagram for E1, E2, and E3
on page13.
Figure 5 illustrates the pulse output format with positive
active energy and negative reactive energy.
E1
E2
E3
Figure 5. Active and Reactive energy pulse outputs
17
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