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参数资料
| 型号： | CRD5463PM-Z |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 27/46页 |
| 文件大小： | 0K |
| 描述： | REFERENCE DESIGN FOR POWER METER |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5463 |
| 主要属性： | 单相功率表 |
| 次要属性： | 90 ~ 260 VAC |
| 已供物品： | 模块，适配器，线缆，电源线 |
| 其它名称： | 598-1943 |
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CS5463
6.1.2 Current and Voltage DC Offset Register ( I DCoff , V DCoff )
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
MSB
LSB
-(2 )
2
2
2
2
2
0
2
-1
2
-2
-3
-4
-5
-6
-7
.....
2 -17
2
-18
2
-19
2
-20
2
-21
2
-22
2 -23
Default = 0x000000
The DC Offset registers (I DCoff ,V DCoff ) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system offset compensation. The value is represent-
ed in two's complement notation and in the range of -1.0 ? I DCoff , V DCoff ? 1.0, with the binary point to the right of
the MSB. See Section 7.1.2.1 DC Offset Calibration Sequence on page 37 for more information.
6.1.3 Current and Voltage Gain Register ( I gn , V gn )
Address: 2 (Current Gain); 4 (Voltage Gain)
MSB
LSB
2 1
2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
.....
2 -16
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
Default = 0x400000 = 1.000
The gain registers (I gn ,V gn ) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system gain compensation. The value is in the range
0.0 ? I gn ,V gn < 3.9999, with the binary point to the right of the second MSB.
6.1.4 Cycle Count Register ( Cycle Count )
Address: 5
MSB
LSB
2 23
2 22
2 21
2 20
2 19
2 18
2 17
2 16
.....
2 6
2 5
2 4
2 3
2 2
2 1
2 0
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle . During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024 ? N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
6.1.5 PulseRateE Register ( PulseRateE )
Address: 6
MSB
LSB
-(2 0 )
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
.....
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
2 -23
Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)
PulseRateE sets the frequency of E1, E2, & E3 pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at
full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's comple-
ment notation and in the range is -1.0 ? PulseRateE ? 1.0, with the binary point to the right of the MSB. Negative
values have the same effect as positive. See Section 5.5 Energy Pulse Output on page 17 for more information.
DS678F3
27
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| CRD5490-Z | 功能描述:电源管理IC开发工具 CS5463 Pwr Meas/Mntr Reference Design RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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| CRD5AS-12BB00 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Reverse Conducting Thyristor Medium Power Use |
| CRD5AS-12B-T13B00 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:Reverse Conducting Thyristor Medium Power Use |
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