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参数资料
| 型号： | CS5165GDWR16 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 稳压器 |
| 英文描述： | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 15/21页 |
| 文件大小： | 718K |
| 代理商： | CS5165GDWR16 |
CS5165
http://onsemi.com
3
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
IC Power Input
VCC
16 V
0.3 V
N/A
1.5 A peak, 200 mA DC
Soft Start Capacitor
SS
6.0 V
0.3 V
200 μA
10 μA
Compensation Capacitor
COMP
6.0 V
0.3 V
10 mA
1.0 mA
Voltage Feedback Input
VFB
6.0 V
0.3 V
10 μA
OffTime Capacitor
COFF
6.0 V
0.3 V
1.0 mA
50 mA
Voltage ID DAC Inputs
VID0VID4
6.0 V
0.3 V
1.0 mA
10 μA
HighSide FET Driver
GATE(H)
16 V
0.3 V
1.5 A peak, 200 mA DC
LowSide FET Driver
GATE(L)
16 V
0.3 V
1.5 A peak, 200 mA DC
Enable Input
ENABLE
6.0 V
0.3 V
100 μA
1.0 mA
Power Good Output
PWRGD
6.0 V
0.3 V
10 μA
30 mA
Power Ground
PGND
0 V
1.5 A peak, 200 mA DC
N/A
Logic Ground
LGND
0 V
100 mA
N/A
ELECTRICAL CHARACTERISTICS (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 14 V; 2.8 DAC Code:
(VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 μF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
VCC Supply Current
Operating
1.0 V < VFB < VDAC (max ontime)
No Loads on GATE(H) and GATE(L)
12
20
mA
Sleep Mode
ENABLE = 0 V
300
600
μA
VCC Monitor
Start Threshold
GATE(H) switching
3.75
3.95
4.15
V
Stop Threshold
GATE(H) not switching
3.65
3.87
4.05
V
Hysteresis
StartStop
80
mV
Error Amplifier
VFB Bias Current
VFB = 0 V
0.1
1.0
μA
COMP Source Current
COMP = 1.2 V to 3.6 V; VFB = 2.7 V
15
30
60
μA
COMP CLAMP Voltage
VFB = 2.7 V, Adjust COMP voltage for Comp
current = 50 μA
0.85
1.0
1.15
V
COMP Clamp Current
COMP = 0 V
0.4
1.0
1.6
mA
COMP Sink Current
VCOMP = 1.2 V; VFB = 3.0 V; VSS > 2.5 V
180
400
800
μA
Open Loop Gain
Note 2
50
60
dB
Unity Gain Bandwidth
Note 2
0.5
2.0
MHz
PSRR @ 1.0 kHz
Note 2
60
85
dB
GATE(H) and GATE(L)
High Voltage at 100 mA
Measure VCC GATE
1.2
2.0
V
Low Voltage at 100 mA
Measure GATE
1.0
1.5
V
Rise Time
1.6 V < GATE < (VCC 2.5 V)
40
80
ns
Fall Time
(VCC 2.5 V) > GATE > 1.6 V
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H) < 2.0 V; GATE(L) > 2.0 V
30
65
100
ns
GATE(L) to GATE(H) Delay
GATE(L) < 2.0 V; GATE(H) > 2.0 V
30
65
100
ns
GATE pulldown
Resistor to PGND, Note 2
20
50
115
kΩ
2. Guaranteed by design, not 100% tested in production.
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