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参数资料
| 型号： | CS5165GDWR16 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 稳压器 |
| 英文描述： | 1.5 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 7/21页 |
| 文件大小： | 718K |
| 代理商： | CS5165GDWR16 |
CS5165
http://onsemi.com
15
Figure 21. OVP Response to an InputtoOutput Short
Circuit by Pulling the Input Voltage to Ground
M 5.00 ms
Trace 1 Regulator Output Voltage (1.0 V/div.)
Trace 4 5.0 V from PC Power Supply (2.0 V/div.)
Figure 22. Circuit To Implement A Dedicated OVP
Output Using The CS5165
CS5165
PWRGD
+5.0 V
10 k
Q1
2N3906
2N3904
Q2
20 k
5.0 k
+5.0 V
10 k
10 K
OVP
Q3
2N3906
56 k
15 k
VCORE
R1
R2
Output Enable Circuit
The Enable pin (pin 8) is used to enable or disable the
regulator output voltage, and is consistent with TTL DC
specifications. It is internally pulledup. If pulled low
(below 0.8 V), the output voltage is disabled. At the same
time the Power Good and Soft Start pins are pulled low, so
that when normal operation resumes powerup of the
CS5165 goes through the Soft Start sequence. Upon pulling
the Enable pin low, the internal IC bias is completely shut
off, resulting in total shutdown of the Controller IC.
Power Good Circuit
The Power Good pin (pin 13) is an opencollector signal
consistent with TTL DC specifications. It is externally
pulledup, and is pulled low (below 0.3 V) when the
regulator output voltage typically exceeds ± 8.5% of the
nominal output voltage. Maximum output voltage deviation
before Power Good is pulled low is ± 12%.
Figure 23. PWRGD Signal Becomes Logic High as
VOUT Enters 8.5% of Lower PWRGD Threshold,
VOUT = +2.84 V (DAC = 10111)
Trace 4 VOUT (1.0 V/div.)
Trace 2 PWRGD (2.0 V/div.)
Figure 24. Power Good Response to an Out of
Regulation Condition
Trace 4 VFB (1.0 V/div.)
Trace 2 PWRGD (2.0 V/div.)
Figure 24 shows the relationship between the regulated
output voltage VFB and the Power Good signal. To prevent
Power Good from interrupting the CPU unnecessarily, the
CS5165 has a builtin delay to prevent noise at the VFB pin
from toggling Power Good. The internal time delay is
designed to take about 75 μs for Power Good to go low and
65 μs for it to recover. This allows the Power Good signal to
be completely insensitive to out of regulation conditions that
are present for a duration less than the built in delay (see
Figure 25).
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