参数资料
| 型号： | CS82C37A96 |
| 厂商： | Intersil |
| 文件页数： | 1/24页 |
| 文件大小： | 0K |
| 描述： | IC CMOS DMA CONTROLLER 44PLCC |
| 标准包装： | 500 |
| 应用： | CMOS DMA 控制器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 2mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 带卷 (TR) |
82C37A
Data Sheet
October 25, 2011
FN2967.3
CMOS High Performance
Programmable DMA Controller
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization
feature. DMA requests may be generated by either hardware
or software, and each channel is independently
programmable with a variety of features for flexible
operation.
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
Ordering Information
PART NUMBER
Features
? Compatible with the NMOS 8237A
? Four Independent Maskable Channels with
Autoinitialization Capability
? Cascadable to any Number of Channels
? High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
? Memory-to-Memory Transfers
? Static CMOS Design Permits Low Power Operation
- ICCSB = 10 μ A Maximum
- ICCOP = 2mA/MHz Maximum
? Fully TTL/CMOS Compatible
? Internal Registers may be Read from Software
? Pb-Free Plus Anneal Available (RoHS Compliant)
PART
PART
TEMP
PKG.
5MHz
MARKING
8MHz
PART MARKING
12.5MHz
MARKING
PACKAGE
RANGE (°C)
DWG. #
CP82C37A-5 CP82C37A-5
0 to +70
40 Ld PDIP
E40.6
CS82C37A
CS82C37A
CS82C37A-1296
CS82C37A -12
0 to +70
44 Ld PLCC
N44.65
(Note 1)
(Tape&Reel)
CS82C37AZ
CS82C37AZ
0 to +70
44 Ld PLCC
N44.65
(Note 2)
(Pb-Free)
IS82C37A-5 IS82C37A -5 IS82C37A
IS82C37A
-40 to +85
44 Ld PLCC
N44.65
MD82C37A/B
MD82C37A/B
-55 to +125 40 Ld CDIP
F40.6
5962-9054302MQA 5962-9054302MQA
SMD#
F40.6
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1997, 2002, 2006, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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