参数资料
| 型号： | CS82C37A96 |
| 厂商： | Intersil |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC CMOS DMA CONTROLLER 44PLCC |
| 标准包装： | 500 |
| 应用： | CMOS DMA 控制器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 2mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 带卷 (TR) |
82C37A
edge. Status Bits 4-7 are cleared upon RESET or Master
Clear.
Status Register
Temporary Register - The Temporary register is used to
hold data during memory-to-memory transfers. Following the
completion of the transfers, the last byte moved can be read
by the microprocessor. The Temporary register always
7 6 5 4 3 2 1 0
BIT NUMBER
1 Channel 0 has reached TC
1 Channel 1 has reached TC
1 Channel 2 has reached TC
1 Channel 3 has reached TC
1 Channel 0 request
1 Channel 1 request
1 Channel 2 request
1 Channel 3 request
contains the last byte transferred in the previous memory-to-
memory operation, unless cleared by a Reset or Master
Clear.
OPERATION
Read Status Register
Write Command Register
Read Request Register
Write Request Register
Read Command Register
Write Single Mask Bit
Read Mode Register
Write Mode Register
Set First/Last F/F
Clear First/Last F/F
Read Temporary Register
Master Clear
Clear Mode Reg. Counter
Clear Mask Register
Read All Mask Bits
Write All Mask Bits
A3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IOR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
IOW
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES
Software Commands
There are special software commands which can be
executed by reading or writing to the 82C37A. These
commands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
Clear First/Last Flip-Flop - This command is executed
prior to writing or reading new address or word count
information to the 82C37A. This command initializes the flip-
flop to a known state (low byte first) so that subsequent
accesses to register contents by the microprocessor will
address upper and lower bytes in the correct sequence.
Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
Master Clear - This software instruction has the same effect
as the hardware Reset. The Command, Status, Request,
11
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C37A will enter the idle cycle.
Clear Mask Register - This command clears the mask bits
of all four channels, enabling them to accept DMA requests.
Clear Mode Register Counter - Since only one address
location is available for reading the Mode registers, an
internal two-bit counter has been included to select Mode
registers during read operation. To read the Mode registers,
first execute the Clear Mode Register Counter command,
then do consecutive reads until the desired channel is read.
Read order is channel 0 first, channel 3 last. The lower two
bits on all Mode registers will read as ones.
FN2967.3
October 25, 2011
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