参数资料
| 型号： | CS82C37A96 |
| 厂商： | Intersil |
| 文件页数： | 8/24页 |
| 文件大小： | 0K |
| 描述： | IC CMOS DMA CONTROLLER 44PLCC |
| 标准包装： | 500 |
| 应用： | CMOS DMA 控制器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 2mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 带卷 (TR) |
82C37A
the channel 0 TC bit in the status register nor generate an
EOP, nor set the channel 0 mask bit in this mode. It will
cause an autoinitialization of channel 0, if that option has
been selected.
If full Autoinitialization for a memory-to-memory operation is
desired, the channel 0 and channel 1 word counts must be
set to equal values before the transfer begins. Otherwise, if
channel 0 underflows before channel 1, it will autoinitialize
and set the data source address back to the beginning of the
block. If the channel 1 word count underflows before channel
0, the memory-to-memory DMA service will terminate, and
channel 1 will autoinitialize but channel 0 will not.
In memory-to-memory mode, Channel 0 may be
programmed to retain the same address for all transfers.
This allows a single byte to be written to a block of memory.
This channel 0 address hold feature is selected by setting bit
1 in the Command register.
The 82C37A will respond to external EOP signals during
memory-to-memory transfers, but will only relinquish the
system busses after the transfer is complete (i.e. after an
S24 state). It should be noted that an external EOP cannot
cause the channel 0 Address and Word Count registers to
autoinitialize, even if the Mode register is programmed for
autoinitialization. An external EOP will autoinitialize the
channel 1 registers, if so programmed. Data comparators in
block search schemes may use the EOP input to terminate
the service when a match is found. The timing of memory-to-
memory transfers is found in Figure 13. Memory-to-memory
operations can be detected as an active AEN with no DACK
outputs.
Priority - The 82C37A has two types of priority encoding
available as software selectable options. The first is Fixed
Priority which fixes the channels in priority order based upon
the descending value of their numbers. The channel with the
lowest priority is 3 followed by 2, 1 and the highest priority
channel, 0. After the recognition of any one channel for
service, the other channels are prevented from interfering
with the service until it is completed.
The second scheme is Rotating Priority. The last channel to
get service becomes the lowest priority channel with the
others rotating accordingly. The next lower channel from the
channel serviced has highest priority on the following
request. Priority rotates every time control of the system
busses is returned to the processor.
With Rotating Priority in a single chip DMA system, any
device requesting service is guaranteed to be recognized
after no more than three higher priority services have
occurred. This prevents any one channel from monopolizing
the system.
Regardless of which priority scheme is chosen, priority is
evaluated every time a HLDA is returned to the 82C37A.
Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the 82C37A
can compress the transfer time to two clock cycles. From
Figure 12 it can be seen that state S3 is used to extend the
access time of the read pulse. By removing state S3, the
read pulse width is made equal to the write pulse width and a
transfer consists only of state S2 to change the address and
state S4 to perform the read/write. S1 states will still occur
when A8-A15 need updating (see Address Generation).
Timing for compressed transfers is found in Figure 15. EOP
will output in S2 if compressed timing is selected.
Compressed timing is not allowed for memory-to-memory
transfers.
Address Generation - In order to reduce pin count, the
82C37A multiplexes the eight higher order address bits on
the data lines. State S1 is used to output the higher order
address bits to an external latch from which they may be
placed on the address bus. The falling edge of Address
Strobe (ADSTB) is used to load these bits from the data lines
to the latch. Address Enable (AEN) is used to enable the bits
onto the address bus through a three-state enable. The
lower order address bits are output by the 82C37A directly.
Lines A0-A7 should be connected to the address bus. Figure
12 shows the time relationships between CLK, AEN,
ADSTB, DB0-DB7 and A0-A7.
During Block and Demand Transfer mode service, which
include multiple transfers, the addresses generated will be
sequential. For many transfers the data held in the external
address latch will remain the same. This data need only
change when a carry or borrow from A7 to A8 takes place in
the normal sequence of addresses. To save time and speed
transfers, the 82C37A executes S1 states only when
updating of A8-A15 in the latch is necessary. This means for
long services, S1 states and Address Strobes may occur
only once every 256 transfers, a savings of 255 clock cycles
for each 256 transfers.
Programming
Rotating Priority
1st
SERVICE
Highest 0
2nd
SERVICE
2
Service
3rd
SERVICE
3
Service
The 82C37A will accept programming from the host
processor anytime that HLDA is inactive, and at least one
rising clock edge has occurred after HLDA went low. It is the
responsibility of the host to assure that programming and
Lowest
1
2
3
Service
3
0
1
Request
0
1
2
HLDA are mutually exclusive.
Note that a problem can occur if a DMA request occurs on
an unmasked channel while the 82C37A is being
programmed. For instance, the CPU may be starting to
8
FN2967.3
October 25, 2011
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