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参数资料
| 型号： | CY7C057V-15BBXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172 |
| 封装： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172 |
| 文件页数： | 13/26页 |
| 文件大小： | 713K |
| 代理商： | CY7C057V-15BBXC |
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 20 of 26
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
When reading a semaphore, data lines 0 through 8 output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
Bus Match Operation
The right port of the CY7C057V 32Kx36 dual-port SRAM can be
configured in a 36-bit long-word, 18-bit word, or 9-bit byte format
for data I/O. The data lines are divided into four lanes, each
consisting of 9 bits (byte-size data lines).
The bus match select (BM) pin works with bus size select (SIZE)
to select bus width (long-word, word, or byte) for the right port of
the dual-port device. The data sequencing arrangement is
selected using the word address (WA) and byte address (BA)
input pins. A logic “0” applied to both the bus match select (BM)
Notes
51. BM and SIZE must be configured one clock cycle before operation is guaranteed.
52. In x36 mode WA and BA pins are “Don’t Care.”
53. In x18 mode BA pin is a “Don’t Care.”
54. DQ represents data output of the chip.
Right Port Configuration[51, 52, 53]
BM
SIZE
Configuration
I/O Pins Used
0
x36 (standard)
I/O0–35
0
1
x36 (CE active SEM mode)
I/O0–35
1
0
x18
I/O0–17
1
x9
I/O0–8
Right Port Operation
Configuration
WA
BA
Data Accessed[54]
I/O Pins Used
x36
X
DQ0–35
I/O0–35
x18
0
X
DQ0–17
I/O0–17
x18
1
X
DQ18–35
I/O0–17
x9
0
DQ0–8
I/O0–8
x9
0
1
DQ9–17
I/O0–8
x9
1
0
DQ18–26
I/O0–8
x9
1
DQ27–35
I/O0–8
Left Port Operation
Control Pin
Effect
B0
I/O0–8 Byte control
B1
I/O9–17 Byte control
B2
I/O18–26 Byte control
B3
I/O27–35 Byte control
9
/
BA WA
CY7C056V
CY7C057V
16K/32Kx36
Dual Port
BM SIZE
9
/
9
/
9
/
x9, x18, x36
/
BUS
MODE
x36
/
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| CY7C0830AV-133AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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