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参数资料
| 型号： | CY7C057V-15BBXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172 |
| 封装： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172 |
| 文件页数： | 4/26页 |
| 文件大小： | 713K |
| 代理商： | CY7C057V-15BBXC |
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 12 of 26
Switching Waveforms
Notes
25. R/W is HIGH for read cycles.
26. Device is continuously selected. CE0 = VIL, CE1=VIH, and B0, B1, B2, B3, WA, BA are valid. This waveform cannot be used for semaphore reads.
27. OE = VIL.
28. Address valid prior to or coinciding with CE0 transition LOW and CE1 transition HIGH.
29. To access RAM, CE0 = VIL, CE1=VIH, B0, B1, B2, B3, WA, BA are valid, and SEM = VIH. To access semaphore, CE0 = VIH, CE1=VIL and SEM = VIL or CE0
and SEM=VIL, and CE1= B0 = B1 = B2 = B3, =VIH.
tRC
tAA
tOHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA
Read Cycle No. 1 (Either Port Address Access)[25, 26, 27]
tACE
tLZOE
tDOE
tHZOE
tHZCE
DATA VALID
tLZCE
tPU
tPD
ISB
ICC
DATA OUT
B2, B3, WA, BA
CE0, CE1, B0,B1,
CURRENT
Read Cycle No. 2 (Either Port CE/OE Access)[25, 28, 29]
SELECT VALID
OE
DATA OUT
tRC
ADDRESS
tAA
tOHA
CE0, CE1
tLZCE
tABE
tHZCE
tACE
tLZCE
Read Cycle No. 3 (Either Port)[25, 27, 28, 29]
B0, B1, B2,
B3, WA, BA
BYTE SELECT VALID
CHIP SELECT VALID
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| CY7C0830AV-133AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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