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参数资料
| 型号： | CY7C057V-15BBXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172 |
| 封装： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172 |
| 文件页数： | 9/26页 |
| 文件大小： | 713K |
| 代理商： | CY7C057V-15BBXC |
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 17 of 26
Notes
45. tHA depends on which enable pin (CE0L/CE1L or R/WL) is deasserted first.
46. tINS or tINR depends on which enable pin (CE0L/CE1L or R/WL) is asserted last.
Switching Waveforms (continued)
Interrupt Timing Diagrams
WRITE 3FFF (7FFF for CY7C057V)
tWC
tHA
READ 3FFF
tRC
tINR
WRITE 3FFE (7FFE for CY7C057V)
tWC
Right Side Sets INTL:
Left Side Sets INTR:
Left Side Clears INTL:
READ 3FFE
tINR
tRC
ADDRESSL
R/WL
INTL
OEL
ADDRESSR
R/WR
INTR
ADDRESSR
R/WR
INTR
OER
ADDRESSL
R/WL
INTR
tINS
tHA
tINS
(7FFF for CY7C057V)
(7FFE for CY7C057V)
CE0L, CE1L
CE0R, CE1R
CE0L, CE1L
CHIP SELECT VALID
Right Side Clears INTR:
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C057V-15AXI | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| CY7C057V-15AXC | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| CY7C0832V-167AXC | 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120 |
| CY7C0851AV-133AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C0830AV-133AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133AI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1M-Bit 64K x 18 4.4ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133BBI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C0830AV-167AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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