- 您现在的位置：买卖IC网 > PDF目录295353 > CY7C057V-15BBXC (CYPRESS SEMICONDUCTOR CORP) 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static PDF资料下载
参数资料
| 型号： | CY7C057V-15BBXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172 |
| 封装： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172 |
| 文件页数： | 5/26页 |
| 文件大小： | 713K |
| 代理商： | CY7C057V-15BBXC |
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 13 of 26
Notes
30. R/W must be HIGH during all address transitions.
31. A write occurs during the overlap (tSCE or tPWE) of CE0=VIL and CE1=VIH or SEM=VIL and B0–3 LOW.
32. tHA is measured from the earlier of CE0/CE1 or R/W or (SEM or R/W) going HIGH at the end of Write Cycle.
33. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified tPWE.
34. To access RAM, CE0 = VIL, CE1=SEM = VIH.
35. To access byte B0, CE0 = VIL, B0 = VIL, CE1=SEM = VIH.
To access byte B1, CE0 = VIL, B1 = VIL, CE1=SEM = VIH.
To access byte B2, CE0 = VIL, B2 = VIL, CE1=SEM = VIH.
To access byte B3, CE0 = VIL, B3 = VIL, CE1=SEM = VIH.
36. Transition is measured ±150 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
37. During this period, the I/O pins are in the output state, and input signals must not be applied.
38. If the CE0 LOW and CE1 HIGH or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance
state.
Switching Waveforms (continued)
tAW
tWC
tPWE
tHD
tSD
tHA
CE0, CE1
R/W
OE
DATAOUT
DATA IN
ADDRESS
tHZOE
tSA
tHZWE
tLZWE
Write Cycle No. 1: R/W Controlled Timing[30, 31, 32, 33]
NOTE 37
CHIP SELECT VALID
tAW
tWC
tSCE
tHD
tSD
tHA
R/W
DATA IN
ADDRESS
tSA
Write Cycle No. 2: CE Controlled Timing[30, 31, 32, 38]
CE0, CE1
CHIP SELECT VALID
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C057V-15AXI | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| CY7C057V-15AXC | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| CY7C0832V-167AXC | 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120 |
| CY7C0851AV-133AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C0830AV-133AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133AI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1M-Bit 64K x 18 4.4ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133BBI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C0830AV-167AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
发布紧急采购，3分钟左右您将得到回复。