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参数资料
| 型号： | CY7C057V-15BBXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172 |
| 封装： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172 |
| 文件页数： | 3/26页 |
| 文件大小： | 713K |
| 代理商： | CY7C057V-15BBXC |
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 11 of 26
Data Retention Mode
The CY7C056V and CY7C057V are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip Enable (CE)[23] must be held HIGH during data retention,
within VDD to VDD – 0.2 V.
2. CE must be kept between VDD – 0.2 V and 70% of VDD during
the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VDD reaches the
minimum operating voltage (3.15 volts).
Notes
21. Test conditions used are Load 1.
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE is LOW when CE0 VIL and CE1 VIH.
24. CE = VDD, Vin = VSS to VDD, TA = 25 C. This parameter is guaranteed but not tested.
Busy Timing[21]
tBHC
BUSY HIGH from CE HIGH
–
12
–
15
ns
tPS
Port set-up for priority
5
–
5
–
ns
tWB
R/W LOW after BUSY (Slave)
0
–
0
–
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
11
–
13
–
ns
tBDD[22]
BUSY HIGH to data valid
–
12
–
15
ns
Interrupt Timing[21]–
tINS
INT set time
–
12
–
15
ns
tINR
INT reset time
–
12
–
15
ns
Semaphore Timing
tSOP
SEM flag update pulse (OE or SEM)10
–
10
–
ns
tSWRD
SEM flag write to read time
5
–
5
–
ns
tSPS
SEM flag contention window
5
–
5
–
ns
tSAA
SEM address access time
–
12
–
15
ns
Switching Characteristics Over the Operating Range[13] (continued)
Parameter
Description
CY7C056V
CY7C057V
Unit
-12
-15
Min
Max
Min
Max
Timing
Parameter
Test Conditions[24]
Max
Unit
ICCDR1
@ VDDDR = 2 V
50
A
Data Retention Mode
3.15 V
VCC 2.0 V
VCC to VCC – 0.2 V
VCC
CE
tRC
V
IH
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