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参数资料
| 型号： | CY7C057V-15BBXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172 |
| 封装： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172 |
| 文件页数： | 2/26页 |
| 文件大小： | 713K |
| 代理商： | CY7C057V-15BBXC |
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 10 of 26
Switching Characteristics Over the Operating Range[13]
Parameter
Description
CY7C056V
CY7C057V
Unit
-12
-15
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
12
–
15
–
ns
tAA
Address to data valid
–
12
–
15
ns
tOHA
Output hold from address change
3
–
3
–
ns
tACE[14, 15]
CE LOW to data valid
–
12
–
15
ns
tDOE
OE LOW to data valid
–
8
–
10
ns
0
–
0
–
ns
tHZOE[14, 16, 17, 18] OE HIGH to High Z
–
10
–
10
ns
3
–
3
–
ns
–
10
–
10
ns
tLZBE
Byte Enable to Low Z
3
–
3
–
ns
tHZBE
Byte Enable to High Z
–
10
–
10
ns
tPU[14, 18]
CE LOW to power-up
0
–
0
–
ns
tPD[14, 18]
CE HIGH to power-down
–
12
–
15
ns
tABE[15]
Byte Enable access time
–
12
–
15
ns
Write Cycle
tWC
Write cycle time
12
–
15
–
ns
tSCE[14, 15]
CE LOW to write end
10
–
12
–
ns
tAW
Address valid to write end
10
–
12
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA[15]
Address set-up to write start
0
–
0
–
ns
tPWE
Write pulse width
10
–
12
–
ns
tSD
Data set-up to write end
10
–
10
–
ns
tHD
Data hold from write end
0
–
0
–
ns
tHZWE[17, 18]
R/W LOW to High Z
–
10
–
ns
tLZWE[17, 18]
R/W HIGH to Low Z
3
–
3
–
ns
tWDD[19]
Write pulse to data delay
–
25
–
ns
tDDD[19]
Write data valid to read data valid
–
20
–
25
ns
Busy Timing[20]
tBLA
BUSY LOW from address match
–
12
–
15
ns
tBHA
BUSY HIGH from address mismatch
–
12
–
15
ns
tBLC
BUSY LOW from CE LOW
–
12
–
15
ns
Notes
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH
and 10-pF load capacitance.
14. CE is LOW when CE0 VIL and CE1 VIH
15. To access RAM, CE = L and SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 2.
18. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer
to Read Timing with Busy waveform.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
20. Test conditions used are Load 1.
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