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| 型号： | CY7C1157V18-333BZXI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 2M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件页数： | 20/27页 |
| 文件大小： | 645K |
| 代理商： | CY7C1157V18-333BZXI |
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Document Number: 001-06621 Rev. *D
Revised March 06, 2008
Page 27 of 27
QDR is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All
product and company names mentioned in this document are the trademarks of their respective holders.
CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Document Title: CY7C1146V18/CY7C1157V18/CY7C1148V18/CY7C1150V18, 18-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Document Number: 001-06621
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
430351
See ECN
NXR
New data sheet
*A
461654
See ECN
NXR
Revised the MPNs from
CY7C1157BV18 to CY7C1146V18
CY7C1148BV18 to CY7C1157V18
CY7C1150BV18 to CY7C1148V18
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH,
tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC
Switching Characteristics table
Modified Power Up waveform
*B
497629
See ECN
NXR
Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, in
Operating Range table and in the DC Electrical Characteristics table
Added foot note in page 1
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Changed VREF (max) spec from 0.85V to 0.95V in the DC Electrical Character-
istics table and in the note below the table
Updated note 21 to specify Overshoot and Undershoot Spec
Updated
Θ
JA and ΘJC values
Removed x9 part and its related information
Updated foot note 24
*C
1175245
See ECN
VKN/KKVTMP Converted from preliminary to final
Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed IDD values from 794 mA to 1020 mA for 375 MHz, 733 mA to 920 mA
for 333 MHz, 685 mA to 850 mA for 300 MHz
Changed ISB values from 227 mA to 290 mA for 375 MHz, 212 mA to 260 mA
for 333 MHz, 201 mA to 250 mA for 300 MHz
Changed tCYC(max) spec to 8.4 ns for all speed bins
Changed
Θ
JA value from 13.48 °C/W to 17.2 °C/W
Updated Ordering Information table
*D
2199066
See ECN
VKN/AESA
Added footnote# 20 related to IDD
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C1157V18-375BZC | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1157V18-375BZI | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1157V18-375BZXC | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1157V18-375BZXI | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| CY7C1157V18 | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
相关代理商/技术参数 |
参数描述 |
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| CY7C1163KV18-400BZI | 功能描述:静态随机存取存储器 18MB (1Mx18) 1.8v 400MHz DDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C1163KV18-450BZC | 功能描述:静态随机存取存储器 18MB (1Mx18) 1.8v 450MHz DDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C1163KV18-550BZC | 功能描述:静态随机存取存储器 18MB (1Mx18) 1.8v 550MHz DDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C11651KV18-400BZC | 功能描述:静态随机存取存储器 Sync 静态随机存取存储器 QDR RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C11651KV18-400BZXC | 功能描述:IC SRAM 18MBIT 400MHZ 165-FPBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
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