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参数资料
| 型号： | CY7C1157V18-333BZXI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 2M X 9 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件页数： | 27/27页 |
| 文件大小： | 645K |
| 代理商： | CY7C1157V18-333BZXI |
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Document Number: 001-06621 Rev. *D
Page 9 of 27
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary for the DLL to be
reset in order to lock to the desired frequency. During Power up,
when the DOFF is tied HIGH, the DLL gets locked after 2048
cycles of stable clock.
Application Example
Figure 1 shows two DDR-II+ used in an application.
Figure 1. Application Example
Truth Table
The truth table for the CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 follows. [3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K rising edges.
L – H
L
D(A) at K (t + 1)
↑
D(A + 1) at K (t + 1)
↑
Read Cycle: (2.0 cycle latency)
Load address; wait two cycle; read data on consecutive K and
K rising edges.
L – H
L
H
Q(A) at K (t + 2)
↑
Q(A + 1) at K (t + 2)
↑
NOP: No Operation
L – H
H
X
High-Z
Standby: Clock Stopped
Stopped
X
Previous State
BUS
MASTER
(CPU or ASIC)
DQ
Addresses
Cycle Start
R/W
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
R = 250ohms
LD
R/W
DQ
A
SRAM#1
K
ZQ
CQ/CQ
K
R = 250ohms
LD
R/W
DQ
A
SRAM#2
K
ZQ
CQ/CQ
K
Notes
2. The above application shows two DDR-II+ used.
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
4. Device powers up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the addresses sequence in the burst.
6. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
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| CY7C1157V18-375BZC | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
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