- 您现在的位置：买卖IC网 > PDF目录298976 > CY7C2561KV18-450BZC (CYPRESS SEMICONDUCTOR CORP) 8M X 8 QDR SRAM, 0.37 ns, PBGA165 PDF资料下载
参数资料
| 型号： | CY7C2561KV18-450BZC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 8M X 8 QDR SRAM, 0.37 ns, PBGA165 |
| 封装： | 15 X 13 MM, 1.4 MM HEIGHT, FBGA-165 |
| 文件页数： | 1/29页 |
| 文件大小： | 839K |
| 代理商： | CY7C2561KV18-450BZC |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
72-Mbit QDR-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency) with ODT
PRELIMINARY
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-15887 Rev. *E
Revised April 24, 2009
Features
■ Separate independent read and write data ports
Supports concurrent transactions
■ 550 MHz clock for high bandwidth
■ 4-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-Die Termination (ODT) feature
Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR-II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR-I device with 1 cycle read latency
when DOFF is asserted LOW
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8V± 0.1V; IO VDDQ = 1.4V to VDD
Supports both 1.5V and 1.8V IO supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2561KV18 – 8M x 8
CY7C2576KV18 – 8M x 9
CY7C2563KV18 – 4M x 18
CY7C2565KV18 – 2M x 36
Functional Description
The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and
CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. Similar to QDR-II archi-
tecture, QDR-II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common IO devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR-II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C2561KV18), 9-bit words (CY7C2576KV18), 18-bit
words (CY7C2563KV18), or 36-bit words (CY7C2565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
These devices have an On-Die Termination feature supported
for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Table 1. Selection Guide
Description
550 MHz
500 MHz
450 MHz
400 MHz
Unit
Maximum Operating Frequency
550
500
450
400
MHz
Maximum Operating Current
x8
900
830
760
690
mA
x9
900
830
760
690
x18
920
850
780
710
x36
1310
1210
1100
1000
Note
1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C2566KV18-450BZI | 8M X 8 DDR SRAM, 0.37 ns, PBGA165 |
| CY7C293AL-35WC | 2K X 8 UVPROM, 35 ns, CDIP24 |
| CY7C474-15DI | 32K X 9 OTHER FIFO, 15 ns, CDIP28 |
| CY7C474-15PI | 32K X 9 OTHER FIFO, 15 ns, PDIP28 |
| CZ12010T0050GBK | 0 MHz - 3000 MHz 50 ohm RF/MICROWAVE TERMINATION |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C2562XV18-366BZXC | 功能描述:静态随机存取存储器 72MB (4Mx18) 1.8v 366MHz QDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C2562XV18-450BZXC | 功能描述:静态随机存取存储器 72MB (4Mx18) 1.8v 450MHz QDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C25632KV18-400BZC | 功能描述:静态随机存取存储器 72MB (4Mx18) 1.8v 400MHz QDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C25632KV18-400BZXI | 功能描述:静态随机存取存储器 72MB (4Mx18) 1.8v 400MHz QDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C25632KV18-450BZC | 功能描述:静态随机存取存储器 72MB (4Mx18) 1.8v 450MHz QDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。