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参数资料
| 型号： | CY7C4225-15JI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| 中文描述： | 1K X 18 OTHER FIFO, 10 ns, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 16/25页 |
| 文件大小： | 409K |
| 代理商： | CY7C4225-15JI |
CY7C4425/4205/4215
CY7C4225/4235/4245
16
Depth Expansion Configuration
(with Programmable Flags)
The CY7C42X5 can easily be adapted to applications requir-
ing more than 64/256/512/1024/2048/4096 words of buffering.
Figure2 shows Depth Expansion using three CY7C42X5s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be
tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration.
42X5–23
WRITECLOCK(WCLK)
WRITE ENABLE(WEN)
RESET(RS)
LOAD(LD)
FF
PAF
PAF
FF
EF
PAE
PAE
EF
WXI RXI
FIRSTLOAD(FL)
READCLOCK(RCLK)
READ ENABLE (REN)
OUTPUT ENABLE(OE)
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
PAF
FF
EF
PAE
WXI RXI
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
V
CC
FIRSTLOAD(FL)
PAF
FF
EF
PAE
WXI RXI
WXO RXO
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
V
CC
FIRSTLOAD(FL)
DATAIN (D)
DATAOUT(Q)
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C4225-25AC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25AI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25ASC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25ASI | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
| CY7C4225-25JC | 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C422525AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4225-25AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4225-25JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C4225V-15ASC | 功能描述:IC SYNC FIFO MEM 1KX18 64LQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 - FIFO 系列:CY7C 标准包装:15 系列:74F 功能:异步 存储容量:256（64 x 4） 数据速率:- 访问时间:- 电源电压:4.5 V ~ 5.5 V 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:24-DIP（0.300"，7.62mm） 供应商设备封装:24-PDIP 包装:管件 其它名称:74F433 |
| CY7C4225V-15ASXC | 功能描述:先进先出 1K X18 LO VLTG SYNC 先进先出 COM RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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