参数资料
型号: CY7C4225-15JI
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: DRAM
英文描述: 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
中文描述: 1K X 18 OTHER FIFO, 10 ns, PQCC68
封装: PLASTIC, LCC-68
文件页数: 7/25页
文件大小: 409K
代理商: CY7C4225-15JI
CY7C4425/4205/4215
CY7C4225/4235/4245
7
Notes:
14. .t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK edge.
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
Switching Waveforms
(continued)
Read Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
SKEW2
WEN
t
CLK
t
OHZ
t
REF
t
REF
RCLK
Q
0
–Q
17
EF
REN
WCLK
OE
t
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
42X5–7
[14]
t
RS
t
RSR
Q
0 -
Q
17
RS
t
RSF
t
RSF
t
RSF
OE=1
OE=0
REN,WEN,
LD
EF,PAE
FF,PAF,
HF
42X5–8
Reset Timing
[15]
[16]
相关PDF资料
PDF描述
CY7C4225-25AC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25AI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25ASC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25ASI 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
CY7C4225-25JC 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs
相关代理商/技术参数
参数描述
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