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参数资料
| 型号： | DC939A |
| 厂商： | Linear Technology |
| 文件页数： | 15/42页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2484 |
| 软件下载： | QuikEval System |
| 设计资源： | DC939A Design File DC939A Schematic |
| 标准包装： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 6.8 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2484 |
| 已供物品： | 板 |
| 相关产品： | LTC2484CDD#TRPBF-ND - IC ADC 24BIT 10-DFN LTC2484IDD#TRPBF-ND - IC ADC 24BIT 10-DFN LTC2484IDD#PBF-ND - IC ADC 24BIT 10-DFN LTC2484CDD#PBF-ND - IC ADC 24BIT 10-DFN |
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LTC2484
22
2484fd
APPLICATIONS INFORMATION
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle (see Figure 8).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be oating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automati-
cally selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the rst rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time tEOCtest
after the falling edge of CS (if EOC = 0) or tEOCtest after
EOC goes LOW (if CS is LOW during the falling edge of
EOC). The value of tEOCtest is 12μs if the device is using its
internal oscillator. If fO is driven by an external oscillator
of frequency fEOSC, then tEOCtest is 3.6/fEOSC in seconds. If
CS is pulled HIGH before time tEOCtest, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than tEOCtest, the rst rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 32nd rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the rst
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the rst rising edge of SCK and the
last bit of the conversion result on the 32nd rising edge of
SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between the rst and 32nd rising edge of SCK (see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conver-
sion. If the device has not nished loading the last input
bit (SPD) of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous conguration
is still kept. This is useful for systems not requiring all 32
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-up is not available to restore SCK to a logic HIGH state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2484’s internal pull-up
at pin SCK is disabled. Normally, SCK is not externally
driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting
a LOW signal, the LTC2484’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor
to SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain
in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period dened above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
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