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参数资料
| 型号： | DC939A |
| 厂商： | Linear Technology |
| 文件页数： | 19/42页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2484 |
| 软件下载： | QuikEval System |
| 设计资源： | DC939A Design File DC939A Schematic |
| 标准包装： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 6.8 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2484 |
| 已供物品： | 板 |
| 相关产品： | LTC2484CDD#TRPBF-ND - IC ADC 24BIT 10-DFN LTC2484IDD#TRPBF-ND - IC ADC 24BIT 10-DFN LTC2484IDD#PBF-ND - IC ADC 24BIT 10-DFN LTC2484CDD#PBF-ND - IC ADC 24BIT 10-DFN |
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LTC2484
26
2484fd
APPLICATIONS INFORMATION
Driving the Input and Reference
The input and reference pins of the LTC2484 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplied
equivalent circuit is shown in Figure 11.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, VREF+ or GND)
can be considered to form, together with RSW and CEQ
(see Figure 11), a rst order passive network with a time
constant
τ = (RS + RSW) CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy
if the sampling period is at least 14 times greater than the
input circuit time constant,
τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
When using the internal oscillator, the LTC2484’s front-end
switched-capacitor network is clocked at 123kHz corre-
sponding to an 8.1μs sampling period. Thus, for settling
errors of less than 1ppm, the driving source impedance
should be chosen such that
τ ≤ 8.1μs/14 = 580ns. When an
external oscillator of frequency fEOSC is used, the sampling
period is 2.5/fEOSC and, for a settling error of less than
1ppm,
τ ≤ 0.178/fEOSC.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization of the sensor is possible.
For many applications, the sensor output impedance
combined with external bypass capacitors produces RC
time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kΩ bridge driving
a 0.1μF bypass capacitor has a time constant an order of
magnitude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers
led to increased noise, reduced DC performance (Offset/
Drift), limited input/output swing (cannot digitize signals
near ground or VCC), added system cost and increased
power. The LTC2484 uses a proprietary switching algo-
VREF
+
VIN
+
VCC
RSW (TYP)
10k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
10k
CEQ
12pF
(TYP)
RSW (TYP)
10k
ILEAK
IIN
+
VIN
–
IIN
–
IREF
+
IREF
–
2484 F11
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 fEOSC EXTERNAL OSCILLATOR
GND
RSW (TYP)
10k
Figure 11. LTC2484 Equivalent Analog Input Circuit
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