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参数资料
| 型号： | DK-DEV-3C120N |
| 厂商： | Altera |
| 文件页数： | 55/92页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III EP3C120 |
| 产品培训模块： | Cyclone® III FPGA Designing an IP Surveillance Camera Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色产品： | Cyclone? III FPGA Development Kit |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3C120 |
| 所含物品： | 开发板、通用电源、缆线和软件 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | EP3C120F484I7-ND - IC CYCLONE III FPGA 120K 484FBGA EP3C120F780I7-ND - IC CYCLONE III FPGA 120K 780FBGA 544-2539-ND - IC CYCLONE III FPGA 120K 780FBGA 544-2538-ND - IC CYCLONE III FPGA 120K 484FBGA 544-2528-ND - IC CYCLONE III FPGA 120K 484FBGA 544-2394-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2393-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2392-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2391-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2390-ND - IC CYCLONE III FPGA 119K 484FBGA 更多... |
| 其它名称： | 544-2444 |
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Design Software Tools and Embedded Processing
Quartus II Design Software
Quartus II Design Software Features Summary
Incremental compilation 1
Pin planner
Qsys (replaces SOPC Builder)
Off-the-shelf IP cores
Parallel development
in ASICs 1
Scripting support
Rapid Recompile 1
Physical synthesis
Design space explorer (DSE)
Extensive cross-probing
Optimization advisors
Chip planner
TimeQuest timing analyzer
SignalTap II embedded
logic analyzer 2
System Console
PowerPlay technology
EDA partners
Improves design timing closure and reduces design compilation times up to 70 percent. Supports team-based
design.
Eases the process of assigning and managing pin assignments for high-density and high-pin-count designs.
Automates system development by integrating IP functions and subsystems (collection of IP functions) using a
hierarchical approach and a high-performance interconnect (based on a network-on-a-chip architecture).
Lets you construct your system-level design using IP cores from Altera and from Altera’s third-party IP partners.
Allows for FPGA prototypes to be designed in parallel using the same design software and IP.
Supports command-line operation and Tcl scripting, as well as GUI design.
Maximizes your productivity by reducing your compilation time by 50 percent on average (for a small design
change after a full compile). Improves design timing preservation.
Uses post placement and routing delay knowledge of a design to improve performance.
Increases performance by automatically iterating through combinations of Quartus II software settings to find
optimal results.
Provides support for cross-probing between verification tools and design source files.
Provides design-specific advice to improve performance, resource usage, and power consumption.
Reduces verification time (while maintaining timing closure) by enabling small, post placement and routing
design changes to be implemented in minutes.
Provides native Synopsys ? Design Constraint (SDC) support and allows you to create, manage, and analyze
complex timing constraints and quickly perform advanced timing verification.
Supports the most channels, fastest clock speeds, largest sample depths, and most advanced triggering
capabilities available in an embedded logic analyzer.
Enables you to easily debug your FPGA in real time using read and write transactions. It also enables you to
quickly create a GUI to help monitor and send data into your FPGA.
Enables you to accurately analyze and optimize both dynamic and static power consumption.
Offers EDA software support for synthesis, functional and timing simulation, static timing analysis, board-level
simulation, signal integrity analysis, and formal verification. To see a complete list of partners, visit
1
2
Included in Subscription Edition only.
Available with Talkback feature enabled in Web Edition.
Getting Started Steps
Step 1: Download free Web Edition
Step 2: Get oriented with Quartus II software interactive tutorial
After installation, open the interactive tutorial on the welcome screen.
Step 3: Sign up for training
Altera Product Catalog
?
2013
?
www.altera.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DK-DEV-3CLS200N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP3CLS200F780 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-3SL150N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP3SL150F152 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-3SL150N/ES | 制造商:Altera Corporation 功能描述:KIT DEVELOPMENT STRATIX II ES |
| DK-DEV-4CGX150N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4CGX150 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-4CGX150N | 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX ((NS |
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