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| 型号： | DK-DEV-3C120N |
| 厂商： | Altera |
| 文件页数： | 89/92页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III EP3C120 |
| 产品培训模块： | Cyclone® III FPGA Designing an IP Surveillance Camera Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色产品： | Cyclone? III FPGA Development Kit |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3C120 |
| 所含物品： | 开发板、通用电源、缆线和软件 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | EP3C120F484I7-ND - IC CYCLONE III FPGA 120K 484FBGA EP3C120F780I7-ND - IC CYCLONE III FPGA 120K 780FBGA 544-2539-ND - IC CYCLONE III FPGA 120K 780FBGA 544-2538-ND - IC CYCLONE III FPGA 120K 484FBGA 544-2528-ND - IC CYCLONE III FPGA 120K 484FBGA 544-2394-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2393-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2392-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2391-ND - IC CYCLONE III FPGA 119K 780FBGA 544-2390-ND - IC CYCLONE III FPGA 119K 484FBGA 更多... |
| 其它名称： | 544-2444 |
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References
Glossary
Below is a glossary of helpful terms to bring you up to speed on Altera devices.
Term
Adaptive logic module (ALM)
Configuration via Protocol (CvP)
Embedded HardCopy Blocks
Equivalent LE
Fractional phase-locked loops
(Fractional PLL)
Global clock networks
Hard processor system (HPS)
Logic element (LE)
Macrocells
Memory logic array blocks (MLABs)
On-chip termination (OCT)
Periphery clocks (PCLKs)
Plug & Play Signal Integrity
Programmable Power Technology
Real-time in-system
programming (ISP)
Regional clocks
System on a chip (SoC)
Variable-precision blocks
Definition
Logic building block, used by some Altera devices, which provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided
between two combinational adaptive LUTs (ALUTs).
CvP is a configuration method that enables you to configure the FPGA using industry-standard protocols.
Currently CvP supports the PCIe protocol.
These metal-programmable hard IP blocks deliver up to 14M ASIC gates or up to 700K additional LEs to
harden standard or logic-intensive applications.
Device density represented as a comparable amount of LEs, which uses the 4-input LUT as a basis.
A phase-locked loop (PLL) in the core fabric, fractional PLLs provide increased flexibility as an additional
clocking source for the transceiver, replacing external VCXOs.
Global clocks can drive throughout the entire device, serving as low-skew clock sources for functional
blocks such as ALMs, DSP blocks, TriMatrix memory blocks, and PLLs. See regional clocks and periphery
clocks for more clock network information.
This processor system is a hardened component within the SoC, which comprises a dual-core
ARM Cortex-A9 MPCore processor, a rich set of peripherals, and multiport memory controllers.
This logic building block, used by some Altera devices, includes a 4-input LUT, a programmable register,
and a carry chain connection. See device handbooks for more information.
Similar to LEs, this is the measure of density in MAX series CPLDs.
MLABs are dual-purpose blocks, configurable as regular logic array blocks or as memory blocks.
Support for driver impedance matching and series termination, which eliminates the need for external
resistors, improves signal integrity, and simplifies board design. On-chip series, parallel, and differential
termination resistors are configurable via Quartus II software.
PCLKs are a collection of individual clock networks driven from the periphery of the device. PCLKs can be
used instead of general-purpose routing to drive signals into and out of the device.
This capability, consisting of Altera’s adaptive dispersion engine and hot socketing, lets you change
the position of backplane cards on the fly, without having to manually configure your backplane
equalization settings.
This feature automatically optimizes logic, DSP, and memory blocks for the lowest power at the required
performance. Only the blocks with critical-path logic need to be in high-performance mode; all others are
in low-power mode.
This capability allows you to program a MAX II device while the device is still in operation. The new design
only replaces the existing design when there is a power cycle to the device, so can perform in-field updates
to the MAX II device at any time without affecting the operation of the whole system.
Regional clocks are device quadrant-oriented and provide the lowest clock delay and skew for logic
contained within a single device quadrant.
An SoC is an embedded system that consists of a processor, peripherals, and custom hardware integrated
on a single device.
These integrated blocks provide native support for signal processing of varying precisions—for example,
9x9, 27x27, and 18x36—in a sum or independent mode.
Altera Product Catalog
?
2013
?
www.altera.com
87
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DK-DEV-3CLS200N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP3CLS200F780 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-3SL150N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP3SL150F152 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-3SL150N/ES | 制造商:Altera Corporation 功能描述:KIT DEVELOPMENT STRATIX II ES |
| DK-DEV-4CGX150N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4CGX150 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-4CGX150N | 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX ((NS |
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