参数资料
型号: DK-DEV-3C120N
厂商: Altera
文件页数: 6/92页
文件大小: 0K
描述: KIT DEV CYCLONE III EP3C120
产品培训模块: Cyclone® III FPGA
Designing an IP Surveillance Camera
Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色产品: Cyclone? III FPGA Development Kit
标准包装: 1
系列: Cyclone® III
类型: FPGA
适用于相关产品: EP3C120
所含物品: 开发板、通用电源、缆线和软件
产品目录页面: 606 (CN2011-ZH PDF)
相关产品: EP3C120F484I7-ND - IC CYCLONE III FPGA 120K 484FBGA
EP3C120F780I7-ND - IC CYCLONE III FPGA 120K 780FBGA
544-2539-ND - IC CYCLONE III FPGA 120K 780FBGA
544-2538-ND - IC CYCLONE III FPGA 120K 484FBGA
544-2528-ND - IC CYCLONE III FPGA 120K 484FBGA
544-2394-ND - IC CYCLONE III FPGA 119K 780FBGA
544-2393-ND - IC CYCLONE III FPGA 119K 780FBGA
544-2392-ND - IC CYCLONE III FPGA 119K 780FBGA
544-2391-ND - IC CYCLONE III FPGA 119K 780FBGA
544-2390-ND - IC CYCLONE III FPGA 119K 484FBGA
更多...
其它名称: 544-2444
20 nm Device Portfolio
Arria 10 SX SoC Features
The 20 nm Arria 10 SoCs deliver all the features and benefits of Arria 10 FPGAs plus a second-generation hard processor
system with 87 percent higher processor performance (1.5 GHz dual-core ARM Cortex?-A9 MPCore?) and enhancements,
such as secure boot, three Ethernet Media Access Controller (EMAC) hard IP cores, and 64 bit DDR4 SDRAM support—all while
maintaining full software compatibility with 28 nm SoCs.
Maximum Resource Count for A rria  10 SX SoC 1
10AS016
10AS022
10AS027
10AS032
10AS048
10AS057
10AS066
ALMs
LEs (K)
Registers
M20K memory blocks
M20K memory (Mb)
MLAB memory (Mb)
DSP blocks
18 x 19 multipliers
61,510
160
246,040
440
9
1
156
312
83,730
220
334,920
588
11
1.8
192
382
101,620
270
406,480
750
15
2.4
800
1,660
118,730
320
474,920
891
17
2.8
985
1,970
181,790
480
727,160
1,438
28
4.3
1,368
2,736
217,080
570
868,320
1,800
35
5.0
1,612
3,046
250,540
660
1,002,160
2,133
42
5.7
1,855
3,356
Global clock networks
32
Regional clock networks
8
8
8
8
8
8
16
I/O voltage levels
supported (V)
I/O standards supported
1.2, 1.25, 1.35, 1.8, 2.5, 3.0 2
3 V I/Os Only: 3 V LVTTL, 2.5 V CMOS
DDR and LVDS I/Os: POD12, POD10, Differential POD12, Differential POD10, LVDS, RSDS, mini-LVDS, LVPECL
All I/Os: 1.8 V CMOS, 1.5 V CMOS, 1.2 V CMOS, SSTL-18 (I and II), SSTL-15 (I and II), SSTL-135, SSTL-125,
SSTL-12, HSTL-18 (I and II), HSTL-15 (I and II), HSTL-12 (I and II), HSUL-12, Differential SSTL-18 (I and II),
Differential SSTL-15 (I and II), Differential SSTL-135, Differential SSTL-125, Differential SSTL-12,
Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12
LVDS channels, 1.6 Gbps
(receive/transmit)
120
120
168
168
222
270
270
Embedded DPA circuitry
OCT
3
Series, parallel, and differential
Transceiver count
PCIe hard IP blocks (Gen3)
12
1
12
1
24
2
24
2
36
2
48
2
48
2
Memory devices supported
DDR4, DDR3, DDR2, QDR IV, QDR II+, QDR II+ Xtreme, LPDDR3, LPDDR2, RLDRAM 3, RLDRAM II, LLDRAM II, HMC
1
2
All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com .
3.0 V compliant, requires a 3 V power supply.
4
Altera Product Catalog
?
2013
?
www.altera.com
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