- 您现在的位置：买卖IC网 > PDF目录17123 > DK-DEV-4CGX150N (Altera)KIT DEVELOPMENT CYCLONE IV GX PDF资料下载
参数资料
| 型号： | DK-DEV-4CGX150N |
| 厂商： | Altera |
| 文件页数： | 33/42页 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT CYCLONE IV GX |
| 应用说明： | Cyclone IV Design Guidelines |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 软件下载： | DK-DEV-4CGX150N Kit Install |
| 特色产品： | Cyclone? IV GX FPGA Development Kit |
| 标准包装： | 1 |
| 系列： | CYCLONE® IV GX |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone IV GX |
| 所含物品： | 板，线缆，文档，电源 |
| 其它名称： | 544-2713 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
Chapter 1: Cyclone IV Device Datasheet
1–39
Glossary
December 2013
Altera Corporation
R
RL
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver Input
Waveform
Receiver input waveform for LVDS and LVPECL differential standards:
Receiver input
skew margin
(RSKM)
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
S
Single-ended
voltage-
referenced I/O
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Table 1–46. Glossary (Part 3 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
0 V
V
CM
p
- n
V
ID
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
相关PDF资料 |
PDF描述 |
|---|---|
| AIRD-02-2R7K | INDUCTOR PWR DRUM CORE 2.7UH |
| AIRD-02-1R5K | INDUCTOR PWR DRUM CORE 1.5UH |
| ECC30DJCB | CONN EDGECARD 60PS .100 PRESSFIT |
| D-SCE-1K-4.8-50-S1-9 | HEAT SHRINK SLEEVE MARKER |
| SPX1431S-L/TR | IC VREF SHUNT PREC ADJ 8-SOICN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DK-DEV-4CGX150N | 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX ((NS |
| DK-DEV-4S100G5N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4S100G5F RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-4SE530N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4SE530H35 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-4SGX230N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4SGX230KF40C2N RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-4SGX230N/C2 | 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件状态:过期 类型:FPGA 配套使用产品/相关产品:EP4SGX230KF40C2N 内容:板，线缆，电源 标准包装:1 |
发布紧急采购，3分钟左右您将得到回复。