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| 型号： | DP83848HSQ/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 10/82页 |
| 文件大小： | 0K |
| 描述： | IC TXRX ETHERNET PHYTER 40-LLP |
| 产品培训模块： | PHYTER® Family |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | 以太网 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-LLP-EP（6x6） |
| 包装： | 剪切带 (CT) |
| 配用： | DP83848H-MAU-EK-ND - BOARD EVALUATION DP83848H |
| 其它名称： | *DP83848HSQ/NOPB DP83848HSQCT |
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DP
83
84
8
H
2.3 PHY Address
The 5 PHY address inputs pins are shared with the
RXD[3:0] pins and COL pin as shown below.
The DP83848H can be set to respond to any of 32 possi-
ble PHY addresses via strap pins. The information is
latched into the PHYCR register (address 19h, bits [4:0])
at device power-up and hardware reset. The PHY
Address pins are shared with the RXD and COL pins.
Each DP83848H or port sharing an MDIO bus in a system
must have a unique physical address.
The DP83848H supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address
0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to
PHYCR will not put the device in Isolate Mode. See
Section 2.3.1 for more information.
For further detail relating to the latch-in timing require-
ments of the PHY Address pins, as well as the other hard-
ware configuration pins, refer to the Reset summary in
Since the PHYAD[0] pin has weak internal pull-up resistor
and PHYAD[4:1] pins have weak internal pull-down resis-
tors, the default setting for the PHY address is 00001
(01h).
Refer to Figure 2 for an example of a PHYAD connection
to external components. In this example, the PHYAD
strapping results in address 00011 (03h).
2.3.1 MII Isolate Mode
The DP83848H can be put into MII Isolate mode by writ-
ing to bit 10 of the BMCR register or by strapping in Phys-
ical Address 0. It should be noted that selecting Physical
Address 0 via an MDIO write to PHYCR will not put the
device in the MII isolate mode.
When in the MII isolate mode, the DP83848H does not
respond to packet data present at TXD[3:0], TX_EN inputs
and presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When
in Isolate mode, the DP83848H will continue to respond to
all management transactions.
While in Isolate mode, the PMD output pair will not trans-
mit packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
The DP83848H can Auto-Negotiate or parallel detect to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the
receiver even when the DP83848H is in Isolate mode.
Table 2. PHY Address Mapping
Pin #
PHYAD Function
RXD Function
35
PHYAD0
COL
36
PHYAD1
RXD_0
37
PHYAD2
RXD_1
38
PHYAD3
RXD_2
39
PHYAD4
RXD_3
Figure 2. PHYAD Strapping Example
CO
L
RXD_
0
RXD_
1
RXD_
2
RXD_
3
VCC
2.
2
k
PHY
A
D0
=
1
PHY
A
D1
=
1
PHY
A
D2
=
0
PHY
A
D3
=
0
PHY
A
D4
=
0
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